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參數(shù)資料
| 型號： | SPT7824BIJ |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | ADC |
| 英文描述： | 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CDIP28 |
| 封裝： | SIDE BRAZED, CERAMIC, DIP-28 |
| 文件頁數(shù)： | 4/11頁 |
| 文件大?。?/td> | 118K |
| 代理商： | SPT7824BIJ |
SPT
2
3/11/97
SPT7824
ELECTRICAL SPECIFICATIONS
TA=TMIN - TMAX, VCC=+5.0 V, VEE=-5.2 V, DVCC=+5.0 V, VIN=±2.0 V, VSB=-2.0 V, VST=+2.0 V, fCLK=40 MHz, 50% clock duty cycle, unless otherwise
specified.
TEST
SPT7824A
SPT7824B
PARAMETERS
CONDITIONS
LEVEL
MIN
TYP
MAX
MIN
TYP
MAX UNITS
Resolution
10
Bits
DC Accuracy (+25
°C)
±Full Scale
Integral Nonlinearity
100 kHz Sample Rate
V
±1.0
±1.5
LSB
Differential Nonlinearity
V
±0.5
±0.75
LSB
No Missing Codes
VI
Guaranteed
Analog Input
fCLK=1 MHz
Input Voltage Range
V
±2.0
V
Input Bias Current
VIN=0 V
VI
30
60
30
60
A
Input Bias Current
TA=-55 to +125
°CIV
75
A
Input Resistance
VI
100
300
100
300
k
Input Resistance
TA=-55 to +125
°C
IV
75
300
75
300
k
Input Capacitance
V
5
pF
Input Bandwidth
3 dB Small Signal
V
120
MHz
+FS Error
V
±2.0
LSB
-FS Error
V
±2.0
LSB
Reference Input
fCLK=1 MHz
Reference Ladder Resistance
VI
500
800
500
800
Reference Ladder Tempco
V
0.8
/°C
Timing Characteristics
Maximum Conversion Rate
VI
40
MHz
Overvoltage Recovery Time
V
20
ns
Pipeline Delay (Latency)
IV
1
Clock Cycle
Output Delay
TA=+25
°C
V
14
18
14
18
ns
Aperture Delay Time
TA=+25
°CV
1
ns
Aperture Jitter Time
TA=+25
°C
V
5
ps-RMS
Acquisition Time
TA=+25
°C
V
12
ns
Dynamic Performance
Effective Number of Bits
fIN=1 MHz
8.7
8.2
Bits
fIN=3.58 MHz
8.7
8.2
Bits
fIN=10.0 MHz
7.3
6.9
Bits
ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)1 25
°C
Note:
1.
Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal
applied conditions in typical applications.
Supply Voltages
VCC ...........................................................................+6 V
VEE ........................................................................... -6 V
Input Voltages
Analog Input ............................................... VFB≤VIN≤VFT
VFT, VFB ..............................................................+3.0 V, -3.0 V
Reference Ladder Current ..................................... 12 mA
CLK Input .................................................................. VCC
Output
Digital Outputs .......................................... +30 to -30 mA
Temperature
Operating Temperature ............................ -55 to +125
°C
Junction Temperature1 .............................................. +175
°C
Lead Temperature, (soldering 10 seconds) ........ +300
°C
Storage Temperature ................................ -65 to +150
°C
Typical thermal impedances (unsoldered, in free air): 28L sidebrazed DIP:
θja = 50 °C/W, 28L plastic DIP: θja = 50°C/W,
28L SOIC:
θja = 100 °C/W.
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