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參數(shù)資料
| 型號： | SPT7725BIG |
| 廠商： | SIGNAL PROCESSING TECHNOLOGIES |
| 元件分類： | ADC |
| 英文描述： | 8-BIT, 300 MSPS, FLASH A/D CONVERTER |
| 中文描述： | 1-CH 8-BIT FLASH METHOD ADC, PARALLEL ACCESS, PGA46 |
| 封裝： | PGA-46 |
| 文件頁數(shù)： | 2/12頁 |
| 文件大?。?/td> | 134K |
| 代理商： | SPT7725BIG |
2
8/17/01
SPT7725
ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)
1
25 °C
Note:
1. Operation at any Absolute Maximum Rating is not implied. See
Electrical Specifications for proper nominal applied conditions
in typical applications.
Supply Voltages
Negative Supply Voltage (V
EE
TO GND) –7.0 to +0.5 V
Ground Voltage Differential ....................–0.5 to +0.5 V
Input Voltage
Analog Input Voltage ...............................V
EE
to +0.5 V
Reference Input Voltage ..........................V
EE
to +0.5 V
Digital Input Voltage ................................V
EE
to +0.5 V
Reference Current V
RTF
to V
RBF
........................25 mA
Output
Digital Output Current ...............................0 to –30 mA
Temperature
Operating Temperature,ambient............. –25 to +85 °C
junction ...................... +150 °C
Lead Temperature, (soldering 10 seconds) ..... +300 °C
Storage Temperature............................ –65 to +150 °C
ELECTRICAL SPECIFICATIONS
T
A
= T
MIN
to T
MAX
, V
EE
=–5.2 V, R
Source
=50
, V
RBF
=–2.00 V, V
R2
=–1.00 V, V
RTF
=0.00 V,
CLK
=250 MHz, Duty Cycle=50%, unless otherwise specified.
TEST
CONDITIONS
TEST
LEVEL
SPT7725A
TYP
SPT7725B
TYP
PARAMETERS
MIN
MAX
MIN
MAX
UNITS
DC Accuracy
Integral Linearity Error
Differential Linearity Error
No missing codes
CLK
= 100 kHz
CLK
= 100 kHz
VI
VI
–0.75
–0.75
±0.60
+0.75
+0.75
–0.95
–0.95
±0.80
+0.95
+0.95
LSB
LSB
Guaranteed
Guaranteed
Analog Input
Offset Error V
RT
Offset Error V
RB
Input Voltage Range
Input Capacitance
VI
VI
VI
–30
–30
–2.0
+30
+30
0.0
–30
–30
–2.0
+30
+30
0.0
mV
mV
Volts
Over full
input range
V
V
VI
V
V
V
10
15
250
1,000
210
335
10
15
250
1,000
210
335
pF
k
μA
V/μs
MHz
MHz
Input Resistance
Input Current
Input Slew Rate
Large Signal Bandwidth
Small Signal Bandwidth
Clock Synchronous
Input Currents
500
500
V
IN
=F.S.
V
IN
=500 mV
P-P
V
40
40
μA
Reference Input
Ladder Resistance
Reference Bandwidth
VI
V
100
200
10
300
100
200
10
300
MHz
Timing Characteristics
Maximum Sample Rate
Clock to Data Delay
Output Delay Tempco
CLK-to-Data Ready Delay (t
D
)
Aperture Jitter
Acquisition Time
IV
V
V
V
V
V
250
300
2.4
250
300
2.4
MSPS
ns
ps/°C
ns
ps
ns
2
2
2.0
2.0
5
5
1.5
1.5
Dynamic Performance
Signal-to-Noise Ratio
IN
= 3.58 MHz
IN
= 50 MHz
IN
= 3.58 MHz
IN
= 50 MHz
IN
= 3.58 MHz
IN
= 50 MHz
VI
VI
VI
VI
VI
VI
45
39
47
42
–52
–43
46
39
44
38
46
41
–50
–42
44
37
dB
dB
dB
dB
dB
dB
Total Harmonic Distortion
–48
–40
–46
–39
Signal-to-Noise and Distortion
(SINAD)
44
37
42
35
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| SPT7725BIJ | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:8-BIT, 300 MSPS, FLASH A/D CONVERTER |
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| SPT7730 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:8-BIT, 3.0 MSPS, SERIAL OUTPUT A/D CONVERTER |
| SPT7730SCS | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:8-BIT, 3.0 MSPS, SERIAL OUTPUT A/D CONVERTER |
| SPT7730SCU | 制造商:CADEKA 制造商全稱:CADEKA 功能描述:8-BIT, 3.0 MSPS, SERIAL OUTPUT A/D CONVERTER |
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