參數(shù)資料
型號: SPT7722SIT
廠商: SIGNAL PROCESSING TECHNOLOGIES
元件分類: ADC
英文描述: 8-bit, 250 MSPS A/D Converter with Demuxed Outputs
中文描述: 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP44
封裝: TQFP-44
文件頁數(shù): 10/12頁
文件大小: 217K
代理商: SPT7722SIT
DATA SHEET
SPT7722
10
Rev. 1.0.2 December 2002
Figure 6. DC-Coupled Single-Ended to Differential
Conversion (power supplies and
bypassing are not shown)
Input Protection
All I/O pads are protected with an on-chip protection circuit.
This circuit provides ESD robustness and prevents latchup
under severe discharge conditions without degrading analog
transmission times.
Power Supplies and Grounding
The SPT7722 is operated from a single power supply in the
range of 4.75V to 5.25V. Normal operation is suggested to be
5.0V. All power supply pins should be bypassed as close to
the package as possible. The analog and digital grounds
should be connected together with a ferrite bead as shown in
the typical interface circuit and as close to the ADC as possible.
Power-Down Mode
To save on power, the SPT7722 incorporates a power-down
function. This function is controlled by the signal on pin PD.
When pin PD is set high, the SPT7722 enters the power-down
mode. All outputs are set to high impedance. In the power-
down mode the SPT7722 dissipates 24mW typically.
Common-Mode Voltage Reference Circuit
The SPT7722 has an on-board common-mode voltage reference
circuit (V
CM
). It is 2.5V and is capable of driving 50
μ
A loads
typically. The circuit is commonly used to drive the center
tap of the RF transformer in fully differential applications.
For single-ended applications, this output can be used to
provide the level shifting required for the single-to-differential
converter conversion circuit. Bypass V
CM
to AGND by
external 0.01
μ
F capacitor, as shown in Figure 3.
Clock Input
The clock input on the SPT7722 can be driven by either a
single-ended or double-ended clock circuit and can handle
TTL, PECL, and CMOS signals. When operating at high
sample rates it is important to keep the pulse width of the
clock signal as close to 50% as possible. For TTL/CMOS sin-
gle-ended clock inputs, the rise time of the signal also
becomes an important consideration.
Digital Outputs
The output circuitry of the SPT7722 has been designed to be
able to support three separate output modes. The demuxed
(double-wide) mode supports either parallel aligned or inter-
leaved data output. The single-channel mode is not demuxed
and can support direct output at speeds up to 125 MSPS. The
output format is straight binary (table 1).
Table 1. Output Data Format
Analog Input
+FS
+FS - 1 LSB
+1 FS
-FS + 1 LSB
-FS
Output Code D7–D0
1111 1111
1111 111
1000 000
0000 000
0000 0000
indicates the flickering bit between logic 0 and 1
The data output mode is set using the DMODE1 and
DMODE
2
inputs (pins 32 & 31 respectively). Table 2
describes the mode switching options.
Table 2. Output Data Modes
Output Mode
Parallel Dual Channel Output
Interleaved Dual Channel Output
Single Channel Data Output
(Bank A only 125 MSPS max)
DMODE
1
DMODE
2
0
0
1
0
1
X
Evaluation Board
The EB7721/22 evaluation board is available to aid designers
in demonstrating the full performance of the SPT7722. This
board includes a clock driver and reset circuit, adjustable
references and common mode, a single-ended to differential
input buffer and a single-ended to differential transformer
(1:1). An application note (AN7722) describing the operation
of this board, as well as information on the testing of the
SPT7722, is also available. Contact the factory for price and
availability of the EB7722.
V
CM
R3
(R3)/2
+
Input
Voltage
(±0.5 V)
R3
R
R2
R2
+
+
R
R
R
51
51
R
ADC
V
IN
+
V
IN
15pF
51
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