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參數(shù)資料
| 型號： | SPT7722 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | 8-bit, 250 MSPS A/D Converter with Demuxed Outputs |
| 中文描述： | 8位，250 MSPS的A / D轉(zhuǎn)換器輸出的解多工 |
| 文件頁數(shù)： | 7/12頁 |
| 文件大?。?/td> | 217K |
| 代理商： | SPT7722 |
SPT7722
DATA SHEET
Rev. 1.0.2 December 2002
7
Theory of Operation
The SPT7722 is a three-step subranger. It consists of two
THAs in series at the input, followed by three ADC blocks.
The first block is a three-bit folder with over/under range
detection. The second block consists of two single-bit folding
interpolator stages. There are pipelining THAs between each
ADC block.
The analog decode functions are the input buffer, input
THAs, three-bit folder, folding interpolators, and pipelining
THAs. The input buffer enables the part to withstand rail-to-
rail input signals without latchup or excessive currents and also
performs single-ended to differential conversion. All of the
THAs have the same basic architecture. Each has a differential
pair buffer followed by switched emitter followers driving the
hold capacitors. The input THA also has hold mode feed-
through cancellation devices.
The three MSBs of the ADC are generated in the first three-
bit folder block, the output of which drives a differential
reference ladder which also sets the full-scale input range.
Differential pairs at the ladder taps generate midscale,
quarter and three-quarter scale, overrange, and underrange.
Every other differential pair collector is cross-coupled to
generate the eighth scale zero crossings. The middle ADC
block generates two bits from the folded signals of the
previous stages after pipeline THAs. Its outputs drive more
pipeline THAs to push the decoding of the three LSBs to the
next half clock cycle. The three LSBs are generated in inter-
polators that are latched one full clock cycle after the MSBs.
The digital decode consists of comparators, exclusive of cells
for gray to binary decoding, and/or cells used for mostly
over/under range logic. There is a total of 2.5 clock cycles
latency before the output bank selection. In order to reduce
sparkle codes and maintain sample rate, no more than three
bits at a time are decoded in any half clock cycle.
The output data mode is controlled by the state of the demux
mode inputs. There are three output modes:
All data on bank A with clock rate limited to
one-half maximum
Interleaved mode with data alternately on banks
A and B on alternate clock cycles
Parallel mode with bank A delayed one cycle to
be synchronous with bank B every other clock cycle
If necessary, the input clock is divided by two. The divided
clock selects the correct output bank. The user can synchro-
nize with the divided clock to select the desired output bank
via the differential RESET input.
The output logic family is CMOS with output OV
DD
supply
adjustable from 2.7V to 5.25V. There are also differential
clock output pins that can be used to latch the output data in
single bank mode or to indicate the current output bank in
demux mode.
Finally, a power-down mode is available, which causes the
outputs to become tri-state, and overall power is reduced to
about 24mW. There is a 2V reference to supply common
mode for single-ended inputs that is not shut down in power-
down mode.
V
IN
N–1
N–2
N–3
N
CLK
CLK
D0–D7
(Bank A)
DCLK
OUT
DCLK
OUT
N+2
2.5 CLK Cycles
of Latency
t
ap
N+4
N+5
N+3
N+2
N
N+1
t
pd2
t
pd2
t
pd1
N+1
Figure 1. Single Mode Timing Diagram
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| SPT7722SIT | 8-bit, 250 MSPS A/D Converter with Demuxed Outputs |
| SPT7725BIG | 8-BIT, 300 MSPS, FLASH A/D CONVERTER |
| SPT7725BIJ | 8-BIT, 300 MSPS, FLASH A/D CONVERTER |
| SPT7725BIQ | 8-BIT, 300 MSPS, FLASH A/D CONVERTER |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SPT7722SIT | 功能描述:視頻模擬/數(shù)字化轉(zhuǎn)換器集成電路 8 Bit 250 MSPS ADC RoHS:否 制造商:Texas Instruments 輸入信號類型:Differential 轉(zhuǎn)換器數(shù)量:1 ADC 輸入端數(shù)量:4 轉(zhuǎn)換速率:3 Gbps 分辨率:8 bit 結(jié)構(gòu): 輸入電壓:3.3 V 接口類型:SPI 信噪比: 電壓參考: 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:TCSP-48 封裝:Reel |
| SPT7722SIT_Q | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 8 BIT_ 250 MSPS ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| SPT7722SITX | 功能描述:直流/直流開關(guān)轉(zhuǎn)換器 8 BIT_ 250 MSPS ADC RoHS:否 制造商:STMicroelectronics 最大輸入電壓:4.5 V 開關(guān)頻率:1.5 MHz 輸出電壓:4.6 V 輸出電流:250 mA 輸出端數(shù)量:2 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT |
| SPT7725 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:8-BIT, 300 MSPS, FLASH A/D CONVERTER |
| SPT7725AIG | 制造商:CADEKA 制造商全稱:CADEKA 功能描述:8-BIT, 300 MSPS, FLASH A/D CONVERTER |
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