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1/21/02
SPT7610
TYPICAL INTERFACE CIRCUIT
The typical interface circuit is shown in figure 3. External
reference taps are provided for correcting integral
nonlinearity errors. These taps can be actively driven to
reduce these errors. (See the Reference Inputs discus-
sion below.) The SPT7610 evaluation board application
note contains more details on interfacing the SPT7610.
The function of each pin and external connections to other
components is as follows:
POWER SUPPLY PINS: AV
EE
, AGND, DGND
AV
EE
is the supply pin with AGND as ground for the de-
vice. The AV
EE
power supply pin should be bypassed as
close to the device as possible with a 10 μF tantalum ca-
pacitor, in parallel with 100 pF and .01 μF chip capacitors.
Place the 100 pF chip capacitor closest to the SPT7610.
Digital ground (DGND) is the ground for the ECL outputs
and is to be referenced to the output pulldown voltage and
appropriately bypassed as shown in figure 3.
ANALOG INPUT: V
IN
There are two analog input pins that are tied to the same
point internally. Either one may be used as an analog input
sense and the other for input force. This is convenient for
testing the source signal to see if there is sufficient drive
capability. The pins can also be tied together and driven by
the same source. The SPT7610 is superior to similar de-
vices due to a preamplifier stage before the comparators.
This makes the device easier to drive because it has con-
stant capacitance and induces less slew rate distortion.
CLOCK INPUTS: CLK, NCLK
The clock inputs are designed to be driven differentially
with ECL levels. The duty cycle of the clock should be kept
at 50% to avoid causing larger second harmonics. If this is
not important to the intended application, then duty cycles
other than 50% may be used.
Figure 3
–
Typical Interface Circuit
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