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參數(shù)資料
| 型號： | SPT5420SIM |
| 廠商： | SIGNAL PROCESSING TECHNOLOGIES |
| 元件分類： | DAC |
| 英文描述： | 13-BIT, OCTAL D/A CONVERTER |
| 中文描述： | PARALLEL, WORD INPUT LOADING, 20 us SETTLING TIME, 13-BIT DAC, PQFP44 |
| 封裝： | PLASTIC, MQFP-44 |
| 文件頁數(shù)： | 5/8頁 |
| 文件大?。?/td> | 118K |
| 代理商： | SPT5420SIM |
5
6/26/01
SPT5420
VOLTAGE REFERENCES AND
ANALOG GROUND INPUTS
Three V
REFTXX
and three V
REFBXX
inputs set the output
range of the three corresponding groups of DACs
(0 and 1; 2 through 5; 6 and 7). Four RGND
XX
inputs set
the output offset voltage of the four corresponding groups
of DACs (0 and 1; 2 and 3; 4 and 5; 6 and 7). The formula
for output swing and offset is presented in the
“
Analog
Outputs
”
section below.
DAC ADDRESSING AND LATCHING
Each DAC has an input latch which receives data from the
data bus, and a DAC latch which receives data from the
input latch. The analog output of each DAC corresponds
to the data in its DAC latch. One of the eight input latches
is addressed by the address lines A(2:0) according to
Table I. While
CS
and
WR
are low, the addressed input
latch is transparent and the seven other input latches are
latched. Bringing
CS
or
WR
high latches data into the ad-
dressed input latch. While
LDAC
is low, all eight DAC
latches are transparent. Bringing
LDAC
high latches data
into the DAC latches. While
CS
,
WR
and
LDAC
are low, both
latches are transparent and input data is transferred
directly to the selected DAC. While
CLR
is low, all DAC out-
puts are set to their corresponding RGND
XX
. Bringing
CLR
high returns each DAC
’
s output to the voltage correspond-
ing to the data in each DAC latch.
Table II summarizes this information, and figures 1a and
1b should be referenced for timing limitations.
POWER SUPPLY SEQUENCING
The sequence in which V
DD
, V
SS
and V
CC
come up is not
critical. The reference inputs, V
REFTXX
and V
REFBXX
, must
come on only after V
DD
and V
SS
have been established.
However, they may be turned on prior to V
CC
. The digital
inputs must be driven only after V
DD
, V
SS
and V
CC
have
been established. Reverse the power-on sequence for
power-down.
ANALOG OUTPUTS VS DIGITAL INPUT
CODE
The output voltage range is equal to twice the difference
between V
REFTXX
and V
REFBXX
. The output voltage is
given by:
V
OUT
= 2 X (V
REFB
+[V
REFT
–
V
REFB
] X
INPUT CODE
8192
)
–
V
RGND
CODE = 0
–
8191
Table I – DAC Addressing
Addressed Input
Latch DAC#
0
1
2
3
4
5
6
7
A2
0
0
0
0
1
1
1
1
A1
0
0
1
1
0
0
1
1
A0
0
1
0
1
0
1
0
1
Table II – Control Logic Table
WR
0
1
x
x
x
x
CS
0
x
1
x
x
x
LDAC
x
x
x
0
1
x
CLR
1
1
1
1
1
0
Input Latch DAC Latch
transparent
1
latched
latched
x
x
DAC outputs at RGND
XX
x
x
x
transparent
latched
Note:
1. Only the input latch addressed by A(2:0) is transparent.
The other input latches are latched.
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