參數(shù)資料
型號： SPMC802B-PD09
廠商： Electronic Theatre Controls, Inc.
英文描述： 32-pin General Purpose Microcontroller (OTP)
中文描述： 32引腳的通用微控制器（檢察官）
文件頁數(shù)： 4/27頁
文件大?。?/td> 1041K
代理商： SPMC802B-PD09
SPMC802B
3.1. CPU
The microprocessor of SPMC802B is a SUNPLUS high
performance processor equipped with Accumulator, Program
Counter, X Register, Y Register, Stack Pointer and Processor
Status Register (The same as 6502 instruction‘s structure).
SPMC802B is a fully static CMOS design. The oscillation
frequency could be varied up to 6.0MHz depends on the
application needs.
3.1.1. Block diagram of Sunplus CPU
A
INSTRUCTION
REGISTER
PROCESSOR
STATUS
REGISTER
P
INSTRUCTION
DECODE
PCH
PCL
INPUT DATA
LATCH
IDLI
DATA BUS
BUFFER
INDEX
REGISTER
X
INTERRUPT
LOGIC
TIMING
CONTROL
CLOCK
GENERATOR
ACCUMULATOR
A
ALU
STACK POINT
REGISTER
S
A
REGISTER SECTION
RESET IRQ
NMI
CONTROL SECTION
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
ADDRESS
BUS
LEGEND
= 8BIT LINE
= 1 BIT LINE
D0
D1
D2
D3
D4
D5
D6
D7
CLK 0 IN
R/W
DATA
BUS
RDY
PD
INDEX
REGISTER
Y
3.3. Oscillator
3.2. Memory
3.2.1. Memory map
SPMC802B Supports 4.5K bytes of EPROM with 512 bytes test
ROM. It also has the configurable options can be programmed
by writer for different applications. The addresses for EPROM,
test ROM, and options are located in $0400h ~ $0FFFh and
$1800h ~ $1FFFh. The RAM area is located in $0080h ~
$00FFh. The functional control registers and I/O control registers
are located in $0000h ~ $0013h. A set of system control
registers can be configured through indexed access addresses
$003Eh and $003Fh. The buffers for stack pointer are started
from $01FFh with downward direction. This area is mirrored to
the RAM area $00FFh ~ $0080h. A system control register
named Stack Limit Register (SLR) is used to limit the Stack area to
prevent the override of the normal operating contents in the RAM.
Once the Stack is over the limiter, CPU reset will be generated.
To prevent the illegal accesses on undefined addresses, there is a
qualification block to limit the accesses. The illegal accesses will
generate the CPU reset to restart the program.
3.2.2. NMI, Reset, IRQ vectors
The address of NMI (not provided in this chip), RESET and IRQ
are located from $1FFA to $1FFF. The interrupt vectors should
be specified in the program to have proper operation.
The SPMC802B supports AT-cut parallel resonant oscillated
Crystal /Resonator, or RC oscillator, or external clock sources by
configurable option (select one from those three types). The
design
of
application
circuit
should
follow
the
vendors‘ specifications or recommendations. The diagram listed
below
represents
typical
X’TAL/ROSC
circuits
for
most
applications:
SPMC802B
XI
XO/R
20 pf
20 pf
(a) Crystal or
Ceramic Resonator
Connections
SPMC802B
XI
XO/R
VDD
Rosc
(b) RC Oscillator
Connections
(c) External
Clock Source
Connections
SPMC802B
XI
XO/R
UNCONNECTED
External Clock
Sunplus Technology Co., Ltd.
Proprietary & Confidential
4
AUG. 07, 2002
Version: 1.0
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