參數(shù)資料
型號(hào)： SPMC802B-PD08
廠商： Electronic Theatre Controls, Inc.
英文描述： 32-pin General Purpose Microcontroller (OTP)
中文描述： 32引腳的通用微控制器（檢察官）
文件頁(yè)數(shù)： 10/27頁(yè)
文件大?。?/td> 1041K
代理商： SPMC802B-PD08
SPMC802B
The Timer 1 interrupt and the Comparator interrupt will be
described in detail in section Timer1 & Real Time Interrupt and
section Comparator.
5.6. Timer1 & Real Time Interrupt
The clock input (XI/XO/R pins), f
OSC
, is internally divided by two to
generate CPU clock, f
CPU
, for whole system. Timer 1 clock, f
TM1
,
is come from CPU clock with the divisor either 1 or 4 setting by
configurable option. The timer clock is fed into an 8-bit free-run
timer built as Timer 1 function. Timer 1 Count Register (TCR1) is
used to read out the current counting value of Timer 1. Once
TCR1 is overflow, it will set the corresponding flag and will
generate interrupt for service if the interrupt input is enabled.
The additional counting stages perform the Power On Reset (POR)
cycle for clock settling down during power up, the Real Time
Interrupt (RTI) function for timing applications, and watchdog
Timer for function recovery. The POR and WDT functions are
described in detail in section WDT & Reset.
For Real Time Interrupt, there is a pre-scalar to perform the
periodic timing events. The pre-scalar is defined below. The
timing events will set the flag and will generate interrupt for service
if the interrupt is enabled.
RTI Rate
WDT Reset time (=RTI/8)
rt1:0
Divisor
f
TM1
=f
CPU
/1*
f
TM1
=f
CPU
/4*
Divisor
f
TM1
=f
CPU
/1*
f
TM1
=f
CPU
/4*
00
2048
2.048ms
8.192ms
16384
16.384ms
66ms
01
4096
4.096ms
16.384ms
32768
32.768ms
131ms
10
8192
8.192ms
32.768ms
65536
66ms
262ms
11
16384
16.384ms
65.536ms
131072
131ms
524ms
Note1:
In this example, the CPU clock is f
CPU
= 1.0MHz (f
OSC
= 2.0MHz).
Note2:
*The f
TM1
is selected by configurable option
fsel
.
5.7. Timer2 & PWM
Timer 2 is a re-loadable 8-bit timer. It consists with an 8-bit
prescale counter, a pre-load register, an 8-bit count-up counter,
and a control block. The base clock input for Timer 2 f
TIN2
can be
either from CPU clock f
CPU
, or from external clock through PB6. It
is fed into an 8-bit prescale counter to generate the Timer 2 clock,
f
TM2
. The prescalar for Timer 2 clock is set as 2 to the power of
the value. An 8-bit counter with a Pre-load Register consist the
main counter of Timer 2. Timer 2 Count Register (TCR2) is used
to set up the pre-load value in write mode and to read out the
current counting value in read mode. Once the Timer 2 clock is
enabled, main counter will count up. When Timer 2 rolls over
from $FF to pre-load data, it generates overflow signal and
reloads the pre-load data into the counting stage and counts up
again. The overflow signal will also generate interrupt for service
if the interrupt function is enabled.
The PWM waveform generator consists with a 3-duty cycle PWM
generator, a 64-duty cycle PWM generator, and a control block for
PWM waveform output to PB7. The general I/O function on PB7
will be disabled while the PWM output is enabled. There are two
kinds of waveform output can be selected, fixed 3-duty cycle
waveform output and programmable 64-duty cycle waveform
output. The overflow signal of Timer 2, is the base clock of PWM
generator. It will feed into the 3-duty cycle waveform generator
and the 64-duty cycle waveform generator.
5.8. Comparator
SPMC802B is built with two channels of voltage Comparator. It
can compare the external voltage input coming from PA4 or PA5
with the external voltage reference set up on PB0, or with the
internal voltage reference (1.24V). These two channels
Comparator can be enabled with the setup of comparison criterion
and the reference source, and selectable interrupt input for event
service. The input operating range of the Comparator is 0.2V to
(VDD-0.2)V.
5.9. WAIT & STOP Mode
There are two kinds of clock control mode supported by
SPMC802B as WAIT mode and STOP mode.
The WAIT mode function will disable CPU clock but leave the
timer clock active, if the bit
wait
is set as '1'. Once the system
being entered the WAIT mode, the activated interrupt events will
recover the normal operation immediately from the next address of
WAIT mode interrupt point. To confirm the interrupt events can
wake up the CPU, the corresponding interrupt enable bits must be
set before entering the WAIT mode.
The STOP mode function will disable whole system clock, if the bit
stop
is set as '1'. Once the system being entered the STOP
mode, only the activated external interrupt events (from I/Os) can
Sunplus Technology Co., Ltd.
Proprietary & Confidential
10
AUG. 07, 2002
Version: 1.0
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SPMC802B-PS05 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-pin General Purpose Microcontroller (OTP)
SPMC802B-PS06 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-pin General Purpose Microcontroller (OTP)
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