參數(shù)資料
型號： SPC7290
廠商： 愛普生（中國）有限公司
英文描述： IEEE 1394-1995 Standrd and IEEE 1394a-2000 Standard Compliant Physical Layer(IEEE 1394-1995標準和兼容IEEE 1394a-2000標準物理層電路)
中文描述： 電機及電子學工程師聯(lián)合會1394-1995迄今為止已有和IEEE 1394a - 2000標準的物理層協(xié)會（IEEE 1394-1995標準和兼容個IEEE 1394a - 2000標準物理層電路）
文件頁數(shù)： 4/8頁
文件大?。?/td> 61K
代理商： SPC7290
4
SPC7290F
0A
Pin Name
AV
DD
AV
SS
PV
DD
PV
SS
V
DD
V
SS
OSCV
DD
OSCV
SS
TPA1_P
TPA1_N
TPB1_P
TPB1_N
TPBIAS1
TPA2_P
TPA2_N
TPB2_P
TPB2_N
TPBIAS2
R1, R0
PD
Function
Pin No.
Pin Type
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Differential
Differential
Differential
Differential
Supply
Differential
Differential
Differential
Differential
Supply
Analog
Hysteresis
I/O
–
–
–
–
–
–
–
–
I/O
I/O
I/O
I/O
O
I/O
I/O
I/O
I/O
O
O
I
Analog circuit power supply pin
Analog circuit ground pin
PLL circuit power supply pin
PLL circuit ground pin
Digital circuit power supply pin
Digital circuit ground pin
Oscillation circuit power supply pin
Oscillation circuit ground pin
Port 1, TPA + input/output signal
Port 1, TPA - input/output signal
Port 1, TPB + input/output signal
Port 1, TPB - input/output signal
Port 1, TP bias voltage supply pin
Port 2, TPA + input/output signal
Port 2, TPA - input/output signal
Port 2, TPB + input/output signal
Port 2, TPB - input/output signal
Port 2, TP bias voltage supply pin
6.0kW (
±
1.0%) external basic resistance connection pin
Test pin
Connect it to V
SS
in normal operation.
Bus Manager Contender / LINK-On Pin
On hardware resetting, whether or not the bus manager
function is employed is decided by the condition of this pin.
On receiving the LINK-On packet, this signal is used to
make the LINK layer controller IC active.
Request signal from the LINK layer controller IC
LINK interface interactive control signal
LINK interface interactive data signal
49.152 MHz system clock to the LINK layer controller IC
LINK power status pin
This signal monitors whether the LINK layer controller IC is
active or not.
Power Status pin
These pins set the power class bit of the Self-ID packet.
PS1, PS2 and PS3 correspond to bits 21, 22 and 23 of
the Self_ID packet.
This signal selects either DC or AC connection depending
on whether or not the isolation barrier exists between PHY
and LINK. Connect this pin to V
SS
for DC connection, and
to V
DD
for AC connection.
Test pin
Connect this pin to V
DD
in normal operation.
Reset pin
This pin initializes SPC7290F
0A
when ‘0’.
Set it to ‘1’ in normal operation.
Cable Power Status detection pin
Connect this pin to the cable power via the 240 k
resistance.
30,31,42,51,52
32,33,39,48,49,50
56
57
16,25,26,62
17,18,63,64
61
58
37
36
35
34
38
46
45
44
43
47
41,40
14
BCLKON
19
CMOS
I/O
LREQ
CTL0, CTL1
D0 to D7
SCLK
LPS
1
Hysteresis
Hysteresis
Hysteresis
I
4,5
I/O
I/O
O
I
6,7,8,9,10,11,12,13
2
15
Hysteresis
PS1
PS2
PS3
20,21,22
CMOS
I
XDIRECT
23
CMOS
I
XTEST_MODE
27
CMOS
I
XRST
53
Hysteresis
I
CPS
24
Hysteresis
I
I
PIN DESCRIPTION
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