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參數(shù)資料
| 型號： | SPC7281 |
| 廠商： | 愛普生（中國）有限公司 |
| 英文描述： | IEEE 1394-1995 Link/ Transaction Controller(IEEE1394-1995標準鏈路/處理控制器) |
| 中文描述： | 電機及電子學工程師聯(lián)合會1394-1995鏈接/交易控制器（IEEE1394連接- 1995標準鏈路/處理控制器） |
| 文件頁數(shù)： | 7/8頁 |
| 文件大?。?/td> | 77K |
| 代理商： | SPC7281 |
7
SPC7281F
0A
Pin Name
C33 External Interface (HV
DD
)
XCE6
EA10M2
EA10M1
EA10M0
XWAIT
XRD
XWRH
XWRL
BCLK
C33 External Interface (LV
DD
)
P14
P13
P12
P11
P10
DSIO
Pin No.
I/O
Reset
Functional Description
Remarks
131
164
163
162
145
24
22
23
182
O
I
I
I
I
O
O
O
O
Area 6 chip enable
Area 10 boot mode selection 2
Area 10 boot mode selection 1
Area 10 boot mode selection 0
Wait cycle input
Read signal
Upper byte write signal
Lower byte write signal
Bus clock signal
166
167
168
169
174
175
B
B
B
B
B
B
General input/output port 14 (for ICD)
General input/output port 13 (for ICD)
General input/output port 12 (for ICD)
General input/output port 11 (for ICD)
General input/output port 10 (for ICD)
Serial input/output pin for debugging
: Used when communicating with ICD33
Pin Name
Clock Generator Pin
OSC4
OSC3
Pin No.
I/O
Reset
Functional Description
Remarks
172
171
O
I
High speed oscillation output
High speed oscillation input
(crystal/ceramic oscillation or external clock input)
PLL setting pin 1
PLL setting pin 0
Capacitor connection pin for PLL
PLLS1
PLLS0
PLLC
161
160
158
I
I
-
Pin Name
Test Pin
TI8
TO7
TO6
TO5
TO4
TO3
TO2
TO1
TO0
FLSTST
RAMTST
MonxWait
MonxInt
Power Supply Pin
HV
DD
Pin No.
I/O
Reset
Functional Description
Remarks
121
122
123
124
125
126
127
128
129
55
156
132
120
I
-
-
-
-
-
-
-
-
-
-
-
-
-
Schmidt input (bus holder)
O
O
O
O
O
O
O
O
I
I
O
O
(MSB)
Output pin for testing
Drive capacity: 1 mA
(LSB)
Built-in FLASH test pin
Built-in SRAM test pin
Internal logic xWait monitor pin
Internal logic xInt monitor pin
A pull-down resistor is built in.
A pull-down resistor is built in.
-
P
H power supply (5V)
5,21,37,67,83,130,165,176 (8pins)
L power supply (3.3V)
1,47,93,103,114,139 (6pins)
GND
148,157,159,170,173,180,184
13,29,46,57,75,92,112,116,117,118,119,138(19pins)
LV
DD
-
P
V
SS
-
P
N.C. Pin
N.C.
-
-
2,45,28,91,94,137,140,183 (8pins)
Pin Name
Other pins
ICEMD
X2PSDX
Pin No.
I/O
Reset
Functional Description
Remarks
179
155
I
I
High impedance control: makes all outputs Hi-Z
A pull-down resistor is built in.
Double speed mode setting pin
H: CPU clock=BCLK
×
1
L: CPU clock=BCLK
×
2
NMI input pin
Initial reset
Dividing output which is 1/2 that of SCLK
FLASH test pin. Connect it to H
VDD
when mounting.
XNMI
XRESET
HCLK
TVEP
177
178
181
58
I
I
O
-
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