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參數(shù)資料
| 型號(hào)： | SPC7212 |
| 廠商： | 愛普生（中國(guó)）有限公司 |
| 英文描述： | SCSI-2 Interface Controller IC(SCSI-2 接口控制器) |
| 中文描述： | 的SCSI - 2接口控制器IC（的SCSI - 2接口控制器） |
| 文件頁(yè)數(shù)： | 5/6頁(yè) |
| 文件大?。?/td> | 57K |
| 代理商： | SPC7212 |
5
SPC7212F
0A
Pin number
CPU Interface
28
29
30
31
32
16
17
18
19
21
22
23
24
38
37
35
34
Others
4
5
84
36
15
7
8
12
13
2
10
Pin name
I/O
Function
Remarks
AD0
AD1
AD2
AD3
AD4
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
XCS
XINT
XRD
XWR
Ipu
Address input pins (AD0 to AD4)
Ipu/O
Data pins (BD0 to BD7)
Drive performance 3mA
"
"
"
"
"
"
"
Ispu
Otr
Ispu
Ispu
Chip select signal for internal register access
Interrupt request output signal
Data read signal
Data write signal
Drive performance 6mA
OSCIN
OSCOUT
TESTMON
XRESET
TESTEN
CLKSEL0
CLKSEL1
PLLCT0
PLLCT1
EXCLK
XPLLPD
I
Built-in oscillation circuit input (40, 20, or 22.5 MHz)
Built-in oscillation circuit output
Test monitor output (Usually: open “Low” output)
System reset input signal
Test pin (Usually connects with Low (GND).)
Input clock selection Low(GND): OSCIN/Hi (LV
DD
): EXCLK input
System clock selection Low (GND): PLL output/Hi (LV
DD
): CLKSEL0 selection signal
PLL operation control pin Depends on input clocks.
PLL operation control pin Depends on input clocks.
5 V level external clock input pin (Connects with Low(GND) when not used.)
PLL power-down pin
Low (GND): PLL power-down mode/Hi (LV
DD
): PLL operation
Internal VC0 control pin
Does not connect with IC chips. (Usually: open)
O
O
Ipu
Ipd
I
I
I
I
I
I
Drive performance 2mA
9
VC
NC
0
—
80, 87, 92,
96, 99
HV
DD
: 5v (5)
20, 27, 39,
49, 61
LV
DD
: 3.3V (6)
1, 6, 11,
26, 51, 76
V
SS
: 0v (17)
3, 14, 25, 33,
44, 50, 56, 66,
69, 72, 75, 79,
83, 88, 91, 95,
100
(Note) I:
Is:
Ipu:
Ispu: Pull-up Schmitt input
Ipd:
Pull-down input
HV
DD
P
Power supply for 5 V interfaces
LV
DD
P
Power supply for internal operation
V
SS
P
GND
Input
Schmitt input
Pull-up input
O:
Ood: Open drain output
Otr:
Tri-state output
Output
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