參數(shù)資料
型號(hào): SPC5604PEF0MLL6
廠商: Freescale Semiconductor
文件頁數(shù): 49/104頁
文件大小: 0K
描述: IC MCU 32BIT 512KB FLASH 100LQFP
標(biāo)準(zhǔn)包裝: 90
系列: MPC56xx Qorivva
核心處理器: e200z0h
芯體尺寸: 32-位
速度: 64MHz
連通性: CAN,F(xiàn)lexRay,LIN,SPI,UART/USART
外圍設(shè)備: DMA,POR,PWM,WDT
輸入/輸出數(shù): 68
程序存儲(chǔ)器容量: 512KB(512K x 8)
程序存儲(chǔ)器類型: 閃存
EEPROM 大?。?/td> 64K x 8
RAM 容量: 40K x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 30x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 125°C
封裝/外殼: 100-LQFP
包裝: 托盤
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale
49
3.8
Power management electrical characteristics
3.8.1
Voltage regulator electrical characteristics
The internal voltage regulator requires an external NPN ballast to be connected as shown in Figure 8. Table 14 contains all
approved NPN ballast components. Capacitances should be placed on the board as near as possible to the associated pins. Care
should also be taken to limit the serial inductance of the VDD_HV_REG, BCTRL and VDD_LV_CORx pins to less than LReg, see
NOTE
The voltage regulator output cannot be used to drive external circuits. Output pins are used
only for decoupling capacitances.
VDD_LV_COR must be generated using internal regulator and external NPN transistor. It is
not possible to provide VDD_LV_COR through external regulator.
For the MPC5604P microcontroller, capacitors, with total values not below CDEC1, should be placed between
VDD_LV_CORx/VSS_LV_CORx close to external ballast transistor emitter. 4 capacitors, with total values not below CDEC2, should
be placed close to microcontroller pins between each VDD_LV_CORx/VSS_LV_CORx supply pairs and the
VDD_LV_REGCOR/VSS_LV_REGCOR pair . Additionally, capacitors with total values not below CDEC3, should be placed between
the VDD_HV_REG/VSS_HV_REG pins close to ballast collector. Capacitors values have to take into account capacitor accuracy,
aging and variation versus temperature.
All reported information are valid for voltage and temperature ranges described in recommended operating condition, Table 8
Figure 8. Configuration with resistor on base
BCTRL
VDD_LV_COR
CDEC3
CDEC2
CDEC1
VDD_HV_REG
BJT(1)
MPC5604P
1 Refer to Table 14.
RB
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