參數(shù)資料
型號(hào): SPC5604BF2MLQ6
廠商: Freescale Semiconductor
文件頁數(shù): 37/109頁
文件大?。?/td> 0K
描述: IC MCU 32BIT 512KB FLASH 144LQFP
標(biāo)準(zhǔn)包裝: 60
系列: MPC56xx Qorivva
核心處理器: e200z0h
芯體尺寸: 32-位
速度: 64MHz
連通性: CAN,I²C,LIN,SCI,SPI
外圍設(shè)備: DMA,POR,PWM,WDT
輸入/輸出數(shù): 123
程序存儲(chǔ)器容量: 512KB(512K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 32K x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 36x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 125°C
封裝/外殼: 144-LQFP
包裝: 托盤
Package pinouts and signal descriptions
MPC5604B/C Microcontroller Data Sheet, Rev. 11.1
Freescale Semiconductor
33
3.13
Recommended operating conditions
Table 12. Recommended operating conditions (3.3 V)
Symbol
Parameter
Conditions
Value
Unit
Min
Max
VSS
SR Digital ground on VSS_HV pins
0
V
VDD1
1 100 nF capacitance needs to be provided between each VDD/VSS pair
SR Voltage on VDD_HV pins with respect to ground
(VSS)
—3.0
3.6
V
VSS_LV2
2 330 nF capacitance needs to be provided between each VDD_LV/VSS_LV supply pair.
SR Voltage on VSS_LV (low voltage digital supply)
pins with respect to ground (VSS)
—VSS0.1 VSS+0.1
V
VDD_BV3
3 400 nF capacitance needs to be provided between VDD_BV and the nearest VSS_LV (higher value may be needed
depending on external regulator characteristics).
SR Voltage on VDD_BV pin (regulator supply) with
respect to ground (VSS)
—3.0
3.6
V
Relative to VDD VDD0.1 VDD+0.1
VSS_ADC
SR Voltage on VSS_HV_ADC (ADC reference) pin
with respect to ground (VSS)
—VSS0.1 VSS+0.1
V
VDD_ADC4
4 100 nF capacitance needs to be provided between VDD_ADC/VSS_ADC pair.
SR Voltage on VDD_HV_ADC pin (ADC reference)
with respect to ground (VSS)
—3.05
5 Full electrical specification cannot be guaranteed when voltage drops below 3.0 V. In particular, ADC electrical
characteristics and I/Os DC electrical specification may not be guaranteed. When voltage drops below VLVDHVL,
device is reset.
3.6
V
Relative to VDD VDD0.1 VDD+0.1
VIN
SR Voltage on any GPIO pin with respect to ground
(VSS)
—VSS0.1
V
Relative to VDD
—VDD+0.1
IINJPAD
SR Injected input current on any pin during overload
condition
55
mA
IINJSUM
SR Absolute sum of all injected input currents during
overload condition
50
TVDD
SR VDD slope to ensure correct power up6
6 Guaranteed by device validation
0.25
V/s
TA C-Grade Part SR Ambient temperature under bias
fCPU 64 MHz
40
85
°C
TJ C-Grade Part SR Junction temperature under bias
40
110
TA V-Grade Part SR Ambient temperature under bias
40
105
TJ V-Grade Part SR Junction temperature under bias
40
130
TA M-Grade Part SR Ambient temperature under bias
40
125
TJ M-Grade Part SR Junction temperature under bias
40
150
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SPC5604BF2VLQ6 制造商:Freescale Semiconductor 功能描述:
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