參數(shù)資料
型號: SPC5604BF2MLH6
廠商: Freescale Semiconductor
文件頁數(shù): 87/109頁
文件大?。?/td> 0K
描述: IC MCU 32BIT 512KB FLASH 64LQFP
標準包裝: 160
系列: MPC56xx Qorivva
核心處理器: e200z0h
芯體尺寸: 32-位
速度: 64MHz
連通性: CAN,I²C,LIN,SCI,SPI
外圍設(shè)備: DMA,POR,PWM,WDT
輸入/輸出數(shù): 45
程序存儲器容量: 512KB(512K x 8)
程序存儲器類型: 閃存
RAM 容量: 32K x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 12x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 125°C
封裝/外殼: 64-LQFP
包裝: 托盤
Pack
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MPC5
604B
/C
Mic
ro
con
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ller
Da
ta
Sh
eet,
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v.
11
.1
Fre
escale
Se
mi
condu
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r
79
10
tHI
SR D Data hold time for inputs
Master mode
0
0
ns
Slave mode
26
——
——
11
tSUO7
CC D Data valid after SCK edge Master mode
32
50
ns
Slave mode
52
160
12
tHO7
CC D Data hold time for outputs Master mode
0
0
ns
Slave mode
8
13
1 Operating conditions: CL = 10 to 50 pF, SlewIN = 3.5 to 15 ns.
2 Maximum value is reached when CSn pad is configured as SLOW pad while SCK pad is configured as MEDIUM. A positive value means that SCK
starts before CSn is asserted. DSPI2 has only SLOW SCK available.
3 Maximum value is reached when CSn pad is configured as MEDIUM pad while SCK pad is configured as SLOW. A positive value means that CSn is
deasserted before SCK. DSPI0 and DSPI1 have only MEDIUM SCK available.
4 The tCSC delay value is configurable through a register. When configuring tCSC (using PCSSCK and CSSCK fields in DSPI_CTARx registers), delay
between internal CS and internal SCK must be higher than
tCSC to ensure positive tCSCext.
5 The tASC delay value is configurable through a register. When configuring tASC (using PASC and ASC fields in DSPI_CTARx registers), delay between
internal CS and internal SCK must be higher than
tASC to ensure positive tASCext.
6 This delay value corresponds to SMPL_PT = 00b which is bit field 9 and 8 of the DSPI_MCR.
7 SCK and SOUT configured as MEDIUM pad
Table 46. DSPI characteristics1 (continued)
No.
Symbol
C
Parameter
DSPI0/DSPI1
DSPI2
Unit
Min
Typ
Max
Min
Typ
Max
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