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參數(shù)資料
| 型號： | SP9602KN |
| 英文描述： | Dual, 12-Bit, Low Power Voltage Output D/A Converter |
| 中文描述： | 雙通道，12位，低功耗，電壓輸出D / A轉(zhuǎn)換 |
| 文件頁數(shù)： | 6/11頁 |
| 文件大小： | 194K |
| 代理商： | SP9602KN |
SP9602DS/02 SP9602 Dual, 12-Bit, Low Power Voltage Output D/A Converter
Copyright 1999 Sipex Corporation
6
DAC
3 TO 7
DECODE
&
5 BITS
8–BIT
LATCH
4-BIT
LATCH
DB11-DB8
DB7-DB4
Ref In
–
+
VOUT
4
4
4
4
4
MUX
4
4
4
8
12
DB3-DB0
INPUT
REGISTER
DAC
REGISTER
LATCH
40K 40K
Figure 1. Detailed Block Diagram (only one DAC shown).
USING THE SP9602 WITH
DOUBLE-BUFFERED INPUTS
Loading Data
To load a 12-bit word to the input register of each
DAC, using a 12-bit data bus, the sequence is as
follows:
1) Set XFER=1, B1/B2=1, CLR=1, WR1=1,
WR2=1, CS=1.
2) Set A (the DAC address) to the desired DAC
— 0 = DAC
; 1 = DAC
3) Set D11 (MSB) through D0 (LSB) to the
desired digital input code.
4) Load the word to the selected DAC by cycling
WR1 and CS through the following sequence:
“1” — “0” — “1”
5) Repeat sequence for each input register.
To load a 12-bit word to the input register of each
DAC, using an 8-bit data bus, the sequence is as
follows:
1) Set XFER=1, B1/B2=1, CLR=1, WR1=1,
WR2=1, CS=1.
2) Set D11 through D4 to the 8 MSB’s of the
desired digital input code.
3) Load the 8 MSB’s of the digital word to the
selected input register by cycling WR1 and CS
through the “1” — “0” — “1” sequence.
4) Reset B1/B2 from “1” —— “0”
5) Set D11 (MSB) through D8 to the 4 LSB’s of
the digital input code.
6) Load the 4 LSB’s by cycling WR1 and CS
through the “1” — “0” — “1” sequence.
7) Repeat sequence for each input register.
TRANSFERRING DATA
To transfer the 12-bit words in the two input registers
to the two DAC registers:
1) Set CLR=1, CS=1, WR1=1.
“0” — “1” sequence.
2) Cycle WR2 and XFER through the “1” —
To set the outputs of the two DAC’s to 0V, cycle WR2
and CLR through the “1” — “0” — “1” sequence,
while keeping XFER = 1.
One Latch, or No Latches
The latches that form the registers can be used in a
“semi-” transparent mode, and a “fully-” transparent
mode. In order to use the
SP9602
in either mode the
user must be interfaced to a 12-bit bus only (B1=1).
The semi–transparent mode is set up such that the first
set of latches is transparent and the second set is used
to latch the incoming data. Data is latched into the
second set rather than the first set, in order to minimize
glitch energy induced from the data formatting. In this
mode, WR1 and CS are tied low, and WR2 and XFER
are used to strobe the data to the addressed DAC. Each
DAC is addressed using the address line A. After the
appropriate DAC has been selected and the data is
settled at the digital inputs, bringing WR2 and XFER
low will transfer the data to the addressed DAC. The
user should be sure to bring XFER and WR2 high
again so that the next selected DAC will not be
overwritten by the last digital code. This mode of
operation may be useful in applications where
preloading of the input registers is not necessary;
Figure 3, top
.
A fully transparent mode is realized by tying WR1,
CS, WR2, and XFER all low. In this mode, anything
that is written on the 12-bit data bus will be passed
directly to the selected DAC. Since both latches are
not being used, the previous digital word will be
overwritten by the new data as soon as the address
changes. This may be useful should the user want to
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SP9602KS | 制造商:SIPEX 制造商全稱:Sipex Corporation 功能描述:Dual, 12-Bit, Low Power Voltage Output D/A Converter |
| SP9604 | 制造商:SIPEX 制造商全稱:Sipex Corporation 功能描述:Quad, 12-Bit, Low Power Voltage Output D/A Converter |
| SP9604JP | 制造商:SIPEX 制造商全稱:Sipex Corporation 功能描述:Quad, 12-Bit, Low Power Voltage Output D/A Converter |
| SP9604JS | 制造商:SIPEX 制造商全稱:Sipex Corporation 功能描述:Quad, 12-Bit, Low Power Voltage Output D/A Converter |
| SP9604KP | 制造商:SIPEX 制造商全稱:Sipex Corporation 功能描述:Quad, 12-Bit, Low Power Voltage Output D/A Converter |
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