參數(shù)資料
型號: SP9601JN
英文描述: 12-Bit, Low Power Voltage Output D/A Converter
中文描述: 12位,低功耗,電壓輸出D / A轉(zhuǎn)換
文件頁數(shù): 3/9頁
文件大?。?/td> 160K
代理商: SP9601JN
SP9601DS/02
SP9601 12-Bit, Low-Power Voltage Output
3
Copyright 2000 Sipex Corporation
SPECIFICATIONS
(continued)
(Typical at 25C; T
MIN
T
A
T
MAX
; V
DD
= +5V, V
SS
= -5V, V
REF
= +3V; CMOS logic level digital inputs; specifications apply to all grades unless otherwise noted.)
PARAMETER
MIN.
TYP.
POWER REQUIREMENTS
V
DD
-J, -K
0.2
-A, -B
0.2
V
-J, -K
0.2
-A, -B
0.2
Power Dissipation
2
SWITCHING
CHARACTERISTICS
CS Setup Time
(t
CSS
)
25
MAX.
UNITS
Note 5
CONDITIONS
+5V,
±
3%; Note 4, 5
0.3
0.45
mA
mA
-5V,
±
3%; Note 4, 5
0.3
0.45
mA
mA
mW
ns
SCLK Fall to CS
Fall Hold Time
(t
CSH0
)
20
ns
SCLK Fall to CS Rise
Hold Time
(t
CSH1
)
0
ns
SCLK High Width
(t
CH
)
40
ns
SCLK Low Width
(t
CL
)
40
ns
DIN Setup Time
(t
DS
)
50
ns
DIN Hold Time
(t
DH
)
0
ns
CS High Pulse Width
(t
CSW
)
ENVIRONMENTAL AND
MECHANICAL
Operating Temperature
-J, -K
-A, -B
Storage
Package
–_N
–_S
30
ns
0
+70
+85
+150
°
C
°
C
°
C
-40
-60
8-pin Plastic DIP
8-pin 0.15" SOIC
Notes:
1.
Integral Linearity, for the
SP9601
, is measured as the arithmetic mean value of the magnitudes of
the greatest positive deviation and the greatest negative deviation from the theoretical value for any
given input condition.
Differential Linearity is the deviation of an output step from the theoretical value of 1 LSB for any two
adjacent digital input codes.
1 LSB = 2*V
REF
/4,096.
V
REF
= 0V.
2.
3.
4.
5.
The following power up sequence is recommended: V
SS
(-5V), Vdd (+5V), V
REF
.
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