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參數(shù)資料
| 型號(hào)： | SP9502JS |
| 英文描述： | Dual, 12-Bit, Voltage Output D/A Converter |
| 中文描述： | 雙通道，12位電壓輸出D / A轉(zhuǎn)換 |
| 文件頁數(shù)： | 4/11頁 |
| 文件大?。?/td> | 230K |
| 代理商： | SP9502JS |
SP9502DS/02
SP9502 Dual, 12-Bit, Voltage Output D/A Converter
4
Copyright 1999 Sipex Corporation
are forced to 1000 0000 0000 and the DAC outputs
will settle to OV. Active low.
Pin 13 — WR1 — Write Input1 — In conjunction
with CS (pin 14), enables input register selection,
and controls the transfer of data from the input bus
to the input registers. Active low.
Pin 14 — CS — Chip Select — Enables writing
data to input registers and/or transferring data from
input bus to DAC registers.
Pin 15 — V
OUT1
— Voltage Output from DAC1.
Pin 16 — DB
11
— Data Bit 11; most significant bit.
Pin 17 — DB
10
— Data Bit 10.
Pin 18 — DB
9
— Data Bit 9.
Pin 19 — DB
8
— Data Bit 8.
Pin 20 — DB
7
— Data Bit 7.
Pin 21 — DB
6
— Data Bit 6.
Pin 22 — DB
5
— Data Bit 5.
Pin 23 — DB
4
— Data Bit 4.
Pin 24 — DB
3
— Data Bit 3.
Pin 25 — DB
2
— Data Bit 2.
Pin 26 — DB
1
— Data Bit 1.
Pin 27 — DB
0
— Data Bit 0; LSB
Pin 28 — N.C. — No Connection.
PINOUT — 28–PIN SOIC & DIP
PIN ASSIGNMENTS
Pin 1 — N.C. — No Connection.
Pin 2 — V
OUT 2
— Voltage Output from DAC2.
Pin 3 — V
SS
— –5V Power Supply Input.
Pin 4 — V
DD
— +5V Power Supply Input.
Pin 5 — CLR — Clear. Gated with WR2 (pin 12).
Active low. Clears both DAC outputs to 0V.
Pin 6 — REF IN2 — Reference Input for DAC2.
Pin 7 — GND — Ground.
Pin 8 — B1/B2 — Byte 1/Byte 2 — Selects Data
Input Format. A logic “1” on pin 8 selects the 12–
bit mode, and all 12 data bits are presented to the
DAC(s) unchanged; a logic “0” selects the 8–bit
mode, and the four LSBs are connected to the four
MSBs, allowing an 8–bit MSB–justified interface.
Pin 9 — A — Address for DAC Selection — A
logic “0” selects DAC 1; a logic “1” selects
DAC 2.
Pin 10 — REF IN1 — Reference Input for DAC1.
Pin 11 — XFER — Transfer. Gated with WR2
(pin 12); loads all DAC registers simultaneously.
Active low.
Pin 12 — WR2 — Write Input 2 — In conjunction
with XFER (pin 11), controls the transfer of data
from the input registers to the DAC registers. In
conjunction with CLR (pin 5), the DAC registers
N.C.
V
OUT2
V
SS
V
DD
CLR
Ref In 2
GND
B1/B2
A
Ref In 1
XFER
WR2
WR1
CS
N.C.
DB
0
DB
1
DB
2
DB
3
DB
4
DB
5
DB
6
DB
7
DB
8
DB
9
DB
10
DB
11
V
OUT1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
SP9502
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SP9502KN | Dual, 12-Bit, Voltage Output D/A Converter |
| SP9502KS | Dual, 12-Bit, Voltage Output D/A Converter |
| SP9504JP | Quad, 12-Bit, Voltage Output D/A Converter |
| SP9504 | Quad, 12-Bit, Voltage Output D/A Converter |
| SP9504JS | Quad, 12-Bit, Voltage Output D/A Converter |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SP9502KN | 制造商:SIPEX 制造商全稱:Sipex Corporation 功能描述:Dual, 12-Bit, Voltage Output D/A Converter |
| SP9502KS | 制造商:SIPEX 制造商全稱:Sipex Corporation 功能描述:Dual, 12-Bit, Voltage Output D/A Converter |
| SP9504 | 制造商:SIPEX 制造商全稱:Sipex Corporation 功能描述:Quad, 12-Bit, Voltage Output D/A Converter |
| SP9504JP | 制造商:SIPEX 制造商全稱:Sipex Corporation 功能描述:Quad, 12-Bit, Voltage Output D/A Converter |
| SP9504JS | 制造商:SIPEX 制造商全稱:Sipex Corporation 功能描述:Quad, 12-Bit, Voltage Output D/A Converter |
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