參數(shù)資料
型號(hào)： SP9472JH
元件分類： ADC
英文描述： 1-CH 12-BIT CONVERTER SUBSYSTEM ADC, PARALLEL ACCESS, CPGA68
封裝： PGA-68
文件頁(yè)數(shù)： 2/4頁(yè)
文件大?。?/td> 1211K
代理商： SP9472JH
SPECIFICATIO N S
At 25C, VCC = ±15V, VDD = 5V, external sample/hold capacitor at 4700pF. All grades are burned-in at +125C for 168 hour.
PA RA M ETERS
M IN.
TY P.
M A X.
UNIT
CONDITIONS
RESOLUTION
12
BITS
INPUT CHA RA CTERISTICS
A NA LOG
V oltage Ranges:
Bipolar
±5, ±10
V
Unipolar
0-10
V
Input Impedence:
On Channel
1010
Off Channel
1010
Input Capacitance:
On Channel
20
pF
Off Channel
20
pF
CM RR7
80
85
–80
dB
(20V DCto1K Hz)
Crosstalk7
–85
-85
–80
dB
(20V P-P, 1K Hz)
Feedthrough7
–85
100
dB
(at 1K Hz)
Offset2
30
5
V
(channel to channel) G=1
Input Bios Current/Channel
1
A
Input V oltage Range3
+10
+11
V
–10
–15
V
DIGITA L
M UX Input Channel Select:
Logic T (4V )
5
30
A
Logic '0' (0.8V )
5
30
A
S/H Command:
Logic'1'(2.4V )
0.2
nA
Logic '0' (0.8V )
5
30
A
A DC Section:
Logic T (2.4V )
10
A
Logic '0' (0.8V )
10
A
TRA NSFER CHA RA CTERISTICS
A CCURA CY
Integral of Linearity4:
JH, SH
±0.024
% FSR
K H, TH
±0,012
% FSR
Differential Linearity4:
JH, SH
±0.024
% FSR
K H, TH
±0.012
% FSR
Gain Error6
G=1
0.7
%
G=100
0.9
%
Unipolar Offset Error6
16
mV
Bipolar Offset Error6
50
mV
Noise Error7
0.5
1
mV P–P
(M easured at S/H Output) G=1
Droop Rate7
50
500
V /mS
Temperature Coefficients:
Unipolar Offset
JH, SH
20
ppm of FSR/C
K H,TH
15
ppm of FSR/C
Bipolar Offset
JH, SH
30
ppm of FSR/C
K H, TH
25
ppm of FSR/C
Full Scale Calibration
JH, SH
60
ppm of FSR/C
K H,TH
35
ppm of FSR/C
SY STEM TIM INGS
A DC Conversion Time:
SP9462/SP9463
15
20
25
S
SP9472/SP9473
9
12
15
S
S/H A perture Delay
50
nS
S/H A perture Uncertainty
2
nS
相關(guān)PDF資料
PDF描述
SP9472KH 1-CH 12-BIT CONVERTER SUBSYSTEM ADC, PARALLEL ACCESS, CPGA68
SDC-14564-315 SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, DIP36
SDC-14564-312 SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, DIP36
SDC-14564-211Q SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, DIP36
SDC-14564-211Y SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, DIP36
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