參數(shù)資料
型號(hào): SP8854E
廠商: Mitel Networks Corporation
英文描述: 2.7GHz Parallel Load Professional Synthesiser(2.7GHz并行負(fù)載專業(yè)合成器)
中文描述: 2.7GHz的并聯(lián)負(fù)載專業(yè)合成器(2.7GHz的并行負(fù)載專業(yè)合成器)
文件頁(yè)數(shù): 3/13頁(yè)
文件大?。?/td> 176K
代理商: SP8854E
3
SP8854E
Pin
Description
These pins are the data inputs to set the RF divider ratio (MN
1
A). High is open circuit on these
pins. Data is transparent from pins to RF buffer when pin 39 (STROBE) is high and frozen in
buffers when pin 39 is low.
Balanced inputs to the RF preamplifier. For single-ended operation the signal is AC-coupled into
pin 13 with pin 14 AC-decoupled to ground (or vice-versa). Pins 13 and 14 are internally DC
biased.
A current sink into this pin is enabled when the lock detect circuit indicates lock. Used to give
an external indication of phase lock.
A capacitor connected to this point determines the lock detect integrator time constant and can
be used to vary the sensitivity of the phase lock indicator.
An external resistor from pin 19 to V
CC
sets the charge pump output current.
The phase detector output is a single ended charge pump sourcing or sinking current to the
inverting input of an external loop filter.
Connected to the non-inverting input of the loop filter to set the optimum DC bias.
Part of the input bus. When this pin is high, the F
REF
/ F
PD
outputs are enabled.
High is open circuit.
This pin controls charge pump output direction. When pin 23 is high, the output sinks current
when F
PD
> F
REF
or when the RF phase leads the reference phase. When pin 23 is low, the
relationship is reversed (see Table 3).
RF divider output pulses. F
PD
= RF input frequency/(M.N
1
A). Pulse width = 8 RF input cycles
(1 cycle of the divide by 8 prescaler output).
Reference divider output pulses. F
REF
= reference input frequency/R. Pulse width = high period
of Ref input.
Leave open circuit if an external reference is used. See Fig. 5 for typical connection for use as
an onboard crystal oscillator.
This pin is the input buffer amplifier for an external reference signal. This amplifier provides the
active element if an onboard crystal oscillator is used.
These pins set the reference divider ratio R. High is open circuit.
When pin 39 is high the A, M, and R counters are held in the reset state and the charge pump
output is disabled. When pin 39 is low the data on the RF data and PD gain pins is fixed in the
buffers, the buffers are loaded into the RF counters and the PD gain control, all the counters are
active, and the charge pump is enabled. High is open circuit.
These pins set the charhe pump current multiplication factor (see Table 2). The data is
transparent into the buffers when pin 39 is high and frozen when pin 39 is low.
High is open circuit.
1-11, 42-44
13 (RF INPUT)
14 (RF INPUT)
17 (LOCK DETECT INPUT)
18 (C-LOCK DETECT)
19 (R
SET
)
20 (CHARGE PUMP OUTPUT)
21 (CHARGE PUMP REF)
22 (F
REF
/ F
PD
ENABLE)
23 (CONTROL DIRECTION)
24
F
PD
if pin 23 is high
F
REF
if pin 23 is low
25
F
PD
if pin 23 is low
F
REF
if pin 23 is high
27 (Ref. oscillator capacitor)
28 (REF IN/XTAL)
29-38
39 (STROBE)
40, 41 (PD gain)
Table 1 Pin descriptions
相關(guān)PDF資料
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相關(guān)代理商/技術(shù)參數(shù)
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