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參數(shù)資料
| 型號(hào)： | SP8852E |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | 2.7GHz Parallel Load Professional Synthesiser(2.7GHz并行負(fù)載專業(yè)合成器) |
| 中文描述： | 2.7GHz的并聯(lián)負(fù)載專業(yè)合成器（2.7GHz的并行負(fù)載專業(yè)合成器） |
| 文件頁(yè)數(shù)： | 7/13頁(yè) |
| 文件大?。?/td> | 174K |
| 代理商： | SP8852E |
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SP8852E
the charge pump outputs when high. During this period the
VCO control voltage will be maintained by the loop filter
components around the loop amplifier, but due to the com-
bined effects of the amplifier input current and charge pump
leakage a gradual change will occur. In order to reduce the
change, the duration of the strobe pulse should be minimised.
Selection of a loop amplifier with low input current will reduce
the VCO voltage droop during the strobe pulse and result in
minimum reference sidebands from the synthesiser.
Reference Input
The reference source can be either driven from an external
sine or square wave source of up to 100MHz or a crystal can
be connected as shown in Fig. 5.
Phase Comparator and Charge Pump
The SP8852E has a digital phase/frequency comparator
driving a charge pump with programmable current output.
The charge pump current level at the minimum gain setting is
approximately equal to the current fed into the R
input, pin
19, and can be increased by programming the bus according
to Table 2 by up to 4 times.
V
CC
2
1·6V
R
SET
Pin 19 current =
Phase detector gain =I
PIN19
(mA)
3
multiplication factor
2
p
mA/rad
Sense bit (bit 12)
1
0
Pin 20
Current source
Current sink
Output for RF phase lag
Table 3
Bit 11
0
0
1
1
Bit 10
0
1
0
1
Phase detector state
Enabled, F
PD
and F
REF
off
Enabled, F
PD
and F
REF
on
Disabled by lock detect, F
PD
and F
REF
on
Disabled, F
PD
and F
REF
on
Table 4
The charge pump connections to the loop amplifier consist
of the charge pump output and the charge pump reference.
The matching of the charge pump up and down currents will
only be maintained if the charge pump output is held at a
voltage equal to the charge pump reference using an
operational amplifier to produce a virtual earth condition at pin
20. The lock detect circuit can drive an LED to give visual
indication of phase lock or provide an indication to the control
system if a pullup resistor is used in place of the LED. A small
capacitor connected form the C-LOCK DETECTOR pin to
ground may be used to delay lock detect indication and
remove glitches produced by momentary phase coincidence
during lock up.
To allow for control direction changes introduced by the
design of the PLL, bit 12 on the input bus address 0 can be
programmed to reverse the sense of the phase detector by
transposing the F
PD
and F
REF
connections. In order that any
external phase detector will also be reversed by this program-
ming bit, the F
and F
outputs are also interchanged by
bit 12 as shown in Table 3.
2
11
2
10
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
2
12
2
13
1
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
0
ADDRESS
PIN 40
BIT 15
PIN 11
BIT 0
NOT USED
PHASE
DETECTOR
STATE
CONTROL
(SEE TABLE 4)
PHASE
DETECTOR
SENSE
CONTROL
(SEE TABLE 3)
10-BIT REFERENCE COUNTER
Fig. 6a Reference word bit allocation
ADDRESS
PHASE
DETECTOR
GAIN
CONTROL
(SEE TABLE 2)
3-BIT
A COUNTER
M COUNTER
Fig. 6b RF division ratio bit allocation
PIN 40
BIT 15
PIN 11
BIT 0
Fig. 6 Programming data format
Bit 15
0
0
1
1
Bit 14
0
1
0
1
Current multiplication factor
1·0
1·5
2·5
4·0
Table 2
The F
and F
signals to the phase detector are
available on pins 24 and 25 and may be used to monitor the
frequency input to the phase detector or used in conjunction
with an external phase detector. These outputs may be
programmed by bits 10 and 11 of word 0 according to Table 4.
State 3, where the outputs are disabled by the lock detect
circuit, is useful where the user wishes to use an external
phase detector. The internal phase/frequency detector may
be used to pull the loop into lock and an automatic switch-over
to the external phase detector made. When the F
and F
outputs are to be used at high frequencies, an external pull
down resistor of minimum value 330
may be connected to
ground to reduce the fall time of the output pulse.
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| SP8853A | 1.3GHz Professional Synthesiser(1.3GHz專業(yè)合成器) |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SP8852E/IG/HCAR | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Zarlink Semiconductor Inc 功能描述: |
| SP8852E/IG/HCAR WAF | 制造商:Zarlink Semiconductor Inc 功能描述: |
| SP8852EIGHCAR | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:2·7GHz Parallel Load Professional Synthesiser |
| SP8852EKGHCAR | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:2·7GHz Parallel Load Professional Synthesiser |
| SP8853 | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:1·3GHz Professional Synthesiser |
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