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參數(shù)資料
| 型號(hào)： | SP8544AS |
| 英文描述： | Two and Four Channel 12-Bit Multiplexed Sampling ADCs |
| 中文描述： | 雙和四通道12位多路采樣ADC |
| 文件頁(yè)數(shù)： | 6/16頁(yè) |
| 文件大?。?/td> | 219K |
| 代理商： | SP8544AS |
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SP8542/8544DS/01 SP8542/8544 Two and Four Channel 12-Bit Multiplexed Sampling ADC's
Copyright 2000 Sipex Corporation
6
1
GAIN ADJ UST
N.C.
2
REF OUT
CH0
4
5
OFFSET ADJ .
6
V
DA
V
SS
7
V
DD
SCLK
8
CS
D
OUT
9
STATUS
SP8542
STATUS OUT
CHIP SELECT
SHUT DOWN
DATA OUT
CLOCK IN
10kOhms
0.01
μ
F*
*Optional filter capacitor is helpful in a noisy pc board application.
3
CH1
AGND
SD
DIN
DATA IN
CH1
CH0
+5V
0.1
μ
F
0.1
μ
F
6.8
μ
F
2kOhms
5kOhms
+
15
14
13
12
11
10
16
Figure 1. Operating Circuit
FEATURES
The
SP8542
and
SP8544
are two and four
channel 12-Bit serial In/Out data acquisition
system. The device contains a high speed 12-bit
analog to digital converter, internal reference,
and a two or four channel input Mux which
drives the internal sample and hold circuit.
The
SP8542
and
SP8544
are fabricated in Sipex'
Bipolar Enhanced CMOS Process that permits
state-of-the-art design using bipolar devices in
the analog/linear section and extremely low
power CMOS in digital/logic section.
CIRCUIT OPERATION
Figure 1 and 2 shows a simple circuit required to
operate the
SP8542
and
SP8544
. Please refer to
the free running mode timing diagram or the
slave mode timing diagram. The conversion is
controlled by the user supplied signals Chip
Select Bar (CS) which selects and deselects the
device, and a system clock (SCLK).
A high level applied to CS asynchronously
clears the internal logic, puts the sample & hold
(CDAC) into sample mode and places the DOUT
(Data Output) pin in a high impedance state.
Conversion is initiated by falling edge on CS in
slave mode at which point the selected input
voltage is held and a conversion is started. A
delay tCS of 90ns is required between the falling
edge of CS and the first rising of SCLK.
The device responds to the shut down signal
asynchronously so that a conversion in progress
will be interrupted and the resulting data will be
erroneous. A 20
μ
Sec delay is required between
the falling edge of shutdown and initiation of
a conversion.
Input Data Format
The
SP8542
requires, in addition to the Chip
Select Bar (CS) and System Clock (SCLK)
signals, one multiplexer configuration bit
(MA0). The
SP8544
requires, in addition to the
Chip Select Bar (CS) and System Clock (SCLK)
signals, two multiplexer configuration bits (MA1
and MA0). These bits are shifted into the DIN
pin, MSB first, during the first two clocks of the
16 clock conversion cycle and configure the
input multiplexer to select the desired input
channel.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SP8542 | Two and Four Channel 12-Bit Multiplexed Sampling ADCs |
| SP8542BN | Two and Four Channel 12-Bit Multiplexed Sampling ADCs |
| SP8542BS | Two and Four Channel 12-Bit Multiplexed Sampling ADCs |
| SP8544JS | Two and Four Channel 12-Bit Multiplexed Sampling ADCs |
| SP9316 | 60 AMP LATCHING POWER RELAY |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SP8544BN | 制造商:SIPEX 制造商全稱(chēng):Sipex Corporation 功能描述:Two and Four Channel 12-Bit Multiplexed Sampling ADCs |
| SP8544BS | 制造商:SIPEX 制造商全稱(chēng):Sipex Corporation 功能描述:Two and Four Channel 12-Bit Multiplexed Sampling ADCs |
| SP8544JN | 制造商:SIPEX 制造商全稱(chēng):Sipex Corporation 功能描述:Two and Four Channel 12-Bit Multiplexed Sampling ADCs |
| SP8544JS | 制造商:SIPEX 制造商全稱(chēng):Sipex Corporation 功能描述:Two and Four Channel 12-Bit Multiplexed Sampling ADCs |
| SP8544KN | 制造商:SIPEX 制造商全稱(chēng):Sipex Corporation 功能描述:Two and Four Channel 12-Bit Multiplexed Sampling ADCs |
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