參數(shù)資料
型號(hào): SP8538BN
英文描述: Micropower Sampling 12-Bit A/D Converter
中文描述: 微采樣12位A / D轉(zhuǎn)換器
文件頁數(shù): 5/12頁
文件大小: 305K
代理商: SP8538BN
SP8538DS/01
SP8538 Micropower Sampling 12-Bit A/D Converter
5
Copyright 1999 Sipex Corporation
The device uses a capacitive DAC architecture
which provides the sampling behavior. This
results in full Nyquist performance at the
fastest
throughput rate (25 KHz) the device is
capable of.
The power supply voltage is variable from 3.0V
to 5.5V which provides supply flexibility. At the
5.0V supply level, conversion plus sampling
time is 40
μ
S and supply current is 250
μ
A (1.25
mW). With a 3.3V supply the conversion plus
sampling time is 170
μ
S and current is reduced
to 150
μ
A (0.5 mW).
The device features automatic shutdown and
will shutdown to a +0.5
μ
A power level as CS
is brought high (de-selected). Power is
proportional to conversion duty cycle and
varies from 250
μ
A at 40
μ
S (Duty cycle =
100%) to 6.25
μ
a at 1.6 ms (Duty cycle = 2.5%).
Examples:
Conversion rate
40
μ
S
80
μ
S
160
μ
S
I
CC
@ 5V
250
μ
A
125
μ
A
62.5
μ
A
Duty Cycle
100%
50%
25%
DESCRIPTION
The
SP8538
is a 12 bit sampling ADC with a
programmable two channel multiplexer and
serial data interface. The ADC samples and
converts 12 bits of data in 40
μ
S with a 5V
supply voltage applied. The
SP8538
will also
operate at a 3.3V supply at 170
μ
S throughput.
The device automatically shuts down to a
+0.5
μ
A (MAX) level as soon as the chip is
deselected (CS=1). Serial data output is
available in an MSB first or LSB first format.
FEATURES
Two program bits, which are shifted into the
device prior to conversion, determine the input
configuration. In the single ended MUX
configuration the input signal will be applied to
either channel 0 or channel 1 and will be ground
referenced. The maximum full scale range is
VCC. In the full differential mode, the signal
will be applied between channel 0 and channel
1. The signals applied at each input may both
be dynamic. This is in contrast with pseudo
differential devices which must have input low
held at a constant level during conversion. The
converter will provide significant common mode
rejection when used in full differential manner.
Both inputs must remain between ground and
VCC for proper conversion.
0DRESSING
Mux Addressing
SGL/DIFF
0
0
1
1
Channel #
0
V
INH
V
INL
V
INH
GND
Comments
ODD/SIGN
0
1
0
1
1
V
INL
V
INH
Full Differential Mode
V
INL
V
INL
Single Ended Mux Mode
V
INH
INPUT VOLTAGE
(V
INH
-V
INL
)*
0 LSB
1 LSB
2048 LSB
4094 LSB
4095 LSB
INPUT VOLTAGE
AT V
CC
/V
REF
= 5V
0V
0.00122V
2.5000V
4.9976V
4.9988V
OUTPUT
CODE
000000000000
000000000001
100000000000
111111111110
111111111111
* See Mux Addressing Table for a definition of V
INH
- V
INL
.
ADC TRANSFER FUNCTION
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