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參數(shù)資料
| 型號： | SP8537 |
| 英文描述： | Micropower Sampling 10-Bit A/D Converter |
| 中文描述： | 微采樣10位A / D轉換器 |
| 文件頁數(shù)： | 6/12頁 |
| 文件大?。?/td> | 220K |
| 代理商： | SP8537 |
6
SP8537DS/03
SP8537 Micropower Sampling 10–Bit Voltage A/D Converter
Copyright 2000 Sipex Corporation
The device is configured such that it
delivers serial data MSB first requiring 15 clock
periods for a full conversion. Please refer to the
timing diagram.
Circuit Operation
The device will ignore any leading zeros
applied to the DIN pin even if CS is low. After
Chip Select Bar (CS) is brought low and the
START bit is clocked in to the converter, the
conversion sequence is initiated. Two additional
bits are clocked in immediately following the
START bit: SGL/DIFF and ODD/SIGN. The
second and third bits clocked in determine the
MUX configuration (see MUX addressing
table). Please refer to the timing diagram.
The SGL/DIFF bit when zero sets the input
MUX for full differential mode and when one,
sets the input MUX for single ended mode. The
ODD/SIGN bit when zero sets channel zero as
the positive input (ground referred for single
ended operation and referred to channel one in
differential mode). With the ODD/SIGN bit one,
channel one will be the positive input (ground
referred for single ended operation and referred
to channel zero in differential mode).
The
SP8537
is a SAR converter with full
differential multiplexed front end, capacitive
DAC, precision comparator, Successive
Approximations Register, control logic and data
output register. After the input is sampled and
held the conversion process begins. The DAC
MSB is set and its output is compared with the
signal input, if the DAC output is less than the
input, the comparator outputs a one which is
latched into the SAR and simultaneously made
available at the ADC serial output pin. Each bit
is tested in a similar manner until the SAR
contains a code which represents the signal input
to within +1/2 LSB. During this process the SAR
content has been shifted out of the ADC serially.
In the MSB first format the data will appear at
the DOUT pin MSB through LSB in 15 clock
periods. Note that the Chip Select Bar pin must
be toggled high between conversions. The DOUT
pin will be in a high impedance state whenever
Chip Select Bar is high. After Chip Select Bar
has been toggled and brought low again, the
converter is ready to accept another START bit
and begin a new conversion.
Full Differential Sampling
The
SP8537
can be configured for single-ended
sampling (i.e. CH0-ground or CH1-ground) or
full differential sampling (CH0-CH1 or CH1-
CH0). In the full differential sampling
configuration, both inputs are sampled and held
simultaneously. Because of the balanced
differential sampling, dynamic common mode
noise riding along the input signal is cancelled
above and beyond DC noise. This is a
significant improvement over psuedo-differential
sampling schemes, where the low side of the
input must remain constant during the conversion,
and therefore only DC noise (i.e. signal offset)
is cancelled. If AC common mode noise is left
to be converted along with the differental
component, the output signal will be degraded.
Full differential sampling allows flexibility in
converting the input signal. If the signal low-side
is already tied to a ground elsewhere in the
system, it can be hardwired to the low side
channel (i.e. CH0 or CH1) which acts as a
signal ground sense, breaking a potential ground
loop. It is also possible to drive the inputs
balanced differential, as long as both inputs are
within the power rails. In this configuration, both
the high and low signals have the same
impedance looking back to ground, and
therefore pick up the same noise along the
physical path from signal source (i.e. sensor,
transducer, battery) to converter. This noise
becomes common mode, and is cancelled out
by the differential sampling of the
SP8537
.
Layout Considerations
To preserve the high resolution and linearity of
the
SP8537
attention must be given to circuit
board layout, ground impedance and bypassing.
A circuit board layout which includes separate
analog and digital ground planes will prevent
the coupling of noise into sensitive converter
circuits and will help to preserve the dynamic
performance of the device. In single ended
mode, the analog input signal should be
referenced to the ground pin of the converter.
This prevents any voltage drops
that occur in
the power supply's common return from appearing
in series with the input signal.
相關PDF資料 |
PDF描述 |
|---|---|
| SP8538JN | RECTIFIER STANDARD SINGLE 1A 50V 50 30A-ifsm 5uA-ir 1.1V-vf MELF 5K/REEL |
| SP8538 | Micropower Sampling 12-Bit A/D Converter |
| SP8538AN | Micropower Sampling 12-Bit A/D Converter |
| SP8538AS | Micropower Sampling 12-Bit A/D Converter |
| SP8538BN | Micropower Sampling 12-Bit A/D Converter |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| SP8538 | 制造商:SIPEX 制造商全稱:Sipex Corporation 功能描述:Micropower Sampling 12-Bit A/D Converter |
| SP8538AN | 制造商:SIPEX 制造商全稱:Sipex Corporation 功能描述:Micropower Sampling 12-Bit A/D Converter |
| SP8538AS | 制造商:SIPEX 制造商全稱:Sipex Corporation 功能描述:Micropower Sampling 12-Bit A/D Converter |
| SP8538BN | 制造商:SIPEX 制造商全稱:Sipex Corporation 功能描述:Micropower Sampling 12-Bit A/D Converter |
| SP8538BS | 制造商:SIPEX 制造商全稱:Sipex Corporation 功能描述:Micropower Sampling 12-Bit A/D Converter |
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