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參數(shù)資料
| 型號： | SP8531KS |
| 元件分類： | ADC |
| 英文描述： | 12-Bit Sampling Serial Out Analog to Digital Converter |
| 中文描述： | 12位抽樣模擬數(shù)字轉(zhuǎn)換器系列 |
| 文件頁數(shù)： | 5/16頁 |
| 文件大小： | 256K |
| 代理商： | SP8531KS |
SP8531DS/01 SP8531 12-Bit Sampling Serial Out Analog to Digital Converter
Copyright 1999 Sipex Corporation
5
CIRCUIT OPERATION
Figure 1 shows a simple circuit required to
operate the
SP8531
. The conversion is
controlled by the user supplied signal Chip
Select Bar (CS) which selects and deselects the
device, and a system clock (SCLK).
A high level applied to CS asynchronously
clears the internal logic, puts the sample & hold
(CDAC) into sample mode and places the DOUT
(Data Output) pin in a high impedance state.
Conversion is initiated by falling edge on CS in
slave mode at which point the input voltage is
held and a conversion is started. A delay of 90ns
is required between the falling edge of CS and
the first rising of SCLK.
The device responds to the shut down signal
asynchronously so that a conversion in progress
will be interrupted and the resulting data will
be erroneous. A 20
μ
Sec minimum delay is
required between the falling edge of shut down
and initiation of a conversion.
Data Format
16 bits of data are sent for each conversion. The
data is shipped with 4 leading "0"s, and then 12
bits of data, MSB first. Data changes on the
falling edge of SCLK and is stable on the rising
edge of SCLK.
Continuous stand alone operation is obtained by
holding CS low. In this mode an oscillator is
connected directly to the SCLK pin. The SCLK
signal along with the STATUS output Signal
are used to synchronize the host system with the
converter's data. In this mode there is a single
dead SCLK cycle between the 16th clock of one
conversion and the first clock of the following
conversion for the
SP8531
. At a clock
frequency of 4 MHz the
SP8531
provides a
throughput rate of 235KHz.
In slave mode operation, CS is brought high
between each conversion so that all conversions
are initiated by falling edge on CS.
FEATURES
The
SP8531
is a sampling, 12-Bit serial out
data acquisition system. The device contains a
high speed 12-bit analog to digital converter,
internal reference, and sample and hold
circuitry.
The
SP8531
is fabricated in Sipex' Bipolar
Enhanced CMOS Process that permits state-of-
the-art design using bipolar devices in the
analog/linear section and extremely low power
CMOS in the digital/logic section.
PIN ASSIGNMENTS
Pin 1-N.C.-No Connection
Pin 2-N.C.-No Connection
Pin 3-VIN - Analog Input
Pin 4-AGND-Analog Ground
Pin 5-VSS-Digital Ground
Pin 6-SCLK-Serial Clock Input
Pin 7-DOUT Digital Data Output
Pin 8-STATUS- High During Conversion
Pin 9-CS-Chip Select Bar Input -
High Deselects chip -Low Selects chip
Pin 10-SD-Shutdown Input, logic low=power
up, logic high = powerdown
Pin 11-VDD Digital +5V supply
Pin 12-VDA Analog +5V supply
Pin 13-OffADJ- External Offset Adjust
Pin 14-N.C.-No Connection
Pin 15-REFOUT-Voltage Reference Output
Pin 16-GAINADJ-External Gain Adjustment
16
15
14
13
12
11
10
9
GAIN ADJUST
REF OUT
N.C.
OFFSET ADJ.
V
DA
V
DD
SD
CS
1
2
3
4
5
6
7
8
N.C.
N.C.
V
IN
AGND
V
SS
SCLK
D
OUT
STATUS
SP8531
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相關(guān)代理商/技術(shù)參數(shù) |
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| SP8537 | 制造商:SIPEX 制造商全稱:Sipex Corporation 功能描述:Micropower Sampling 10-Bit A/D Converter |
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| SP8538AS | 制造商:SIPEX 制造商全稱:Sipex Corporation 功能描述:Micropower Sampling 12-Bit A/D Converter |
| SP8538BN | 制造商:SIPEX 制造商全稱:Sipex Corporation 功能描述:Micropower Sampling 12-Bit A/D Converter |
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