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參數(shù)資料
| 型號： | SP8531BS |
| 元件分類： | ADC |
| 英文描述： | 12-Bit Sampling Serial Out Analog to Digital Converter |
| 中文描述： | 12位抽樣模擬數(shù)字轉(zhuǎn)換器系列 |
| 文件頁數(shù)： | 7/16頁 |
| 文件大小： | 256K |
| 代理商： | SP8531BS |
SP8531DS/01 SP8531 12-Bit Sampling Serial Out Analog to Digital Converter
Copyright 1999 Sipex Corporation
7
regulator to any analog components requiring
+5V including the
SP8531
. Noise on the power
supply lines can degrade the converters
performance, especially corrupting are noise
and spikes from a switching power supply.
The ground pins (AGND and VSS) on the
SP8531
are separated internally and should be
connected to each other under the converter.
Applying the technique of using separate
analog and digital ground planes is usually the
best way to preserve dynamic performance and
reduce noise coupling into sensitive converter
circuits. Where any compromise must be made
the common return of the analog input signal
should be referenced to the AGND pin of the
converter. This prevents any voltage drops that
might occur in the power supply's common
return from appearing in series with the input
signal.
Coupling between analog and digital lines should
be minimized by careful layout. For instance, if
analog and digital lines must cross they should
do so at right angles. Parallel analog and digital
lines should be separated from each other by a
trace connected to common.
If external gain and offset potentiometers are
used, the potentiometers and related resistors
should be located as close to the
SP8531
as
possible.
Minimizing “Glitches”
Coupling of external transients into an analog to
digital converter can cause errors which are
difficult to debug. In addition to the above
discussions on layout considerations, bypassing
and grounding, there are several other useful
steps that can be taken to get the best analog
performance from a system using the
SP8531
converter. These potential system problem
sources are particularly important to consider
when developing a new system, and looking for
causes of errors in breadboards.
First, care should be taken to avoid transients
during critical times in the sampling and
conversion process. Since the
SP8531
has a
internal sample/hold function, the signal that
puts the device into hold state (CS going low) is
critical, as it would be on any sample/hold
amplifier. The CS falling edge should have a 5
to 10 ns transition time, low jitter, and have
minimal ringing, especially during the first 20ns
after it falls.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SP8531JN | 12-Bit Sampling Serial Out Analog to Digital Converter |
| SP8531JS | 12-Bit Sampling Serial Out Analog to Digital Converter |
| SP8531KN | 12-Bit Sampling Serial Out Analog to Digital Converter |
| SP8531KS | 12-Bit Sampling Serial Out Analog to Digital Converter |
| SP8537 | Micropower Sampling 10-Bit A/D Converter |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SP8531JN | 制造商:SIPEX 制造商全稱:Sipex Corporation 功能描述:12-Bit Sampling Serial Out Analog to Digital Converter |
| SP8531JS | 制造商:SIPEX 制造商全稱:Sipex Corporation 功能描述:12-Bit Sampling Serial Out Analog to Digital Converter |
| SP8531KN | 制造商:SIPEX 制造商全稱:Sipex Corporation 功能描述:12-Bit Sampling Serial Out Analog to Digital Converter |
| SP8531KS | 制造商:SIPEX 制造商全稱:Sipex Corporation 功能描述:12-Bit Sampling Serial Out Analog to Digital Converter |
| SP8537 | 制造商:SIPEX 制造商全稱:Sipex Corporation 功能描述:Micropower Sampling 10-Bit A/D Converter |
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