參數(shù)資料
型號: SP8400
廠商: Mitel Networks Corporation
英文描述: Very Low Phase Noise Synthesiser Divider
中文描述: 極低的相位噪聲合成器分頻器
文件頁數(shù): 3/6頁
文件大小: 113K
代理商: SP8400
3
SP8400
APPLICATIONS INFORMATION
Circuit description, synthesiser divider
The divider is based on a divide by 8/9 modulus prescaler,
and a 12 stage control counter. This gives minimum fractional
– N division ratio of 64 (56 for general division), and a maximum
division ratio of 4103. The inputs to the control counter are TTL/
CMOS compatible. There is a fixed offset of 8 between the
number on the data lines and the actual division ratio.
The output is one transition only per divide cycle. This
eliminates the problem of where to put the redundant edge
when the divider is used in a fractional–N system, and also
avoids the problem of how to define the output pulse width. This
means that the overall division ratio conventionally defined in
terms of the rate of edges of the same polarity is twice the
selected division ratio.
Fig.4 Test circuit
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SP8400
10nF
10nF
1nF
1nF
2x330R
1nF
RF
TTL/CMOS
MODULUS
CONTROL
TTL/CMOS
MODULUS
CONTROL
V
CC
50R
50R
SIGNAL
GENERATOR
220nF
OUTPUT
Equations for division
The M and A data inputs form a 12 bit number with A0
being the least significant bit and M8 being the most significant
bit.
Definition 1:
Division ratio – (input frequency to output
edges, positive or negative).
= Number loaded + 8
Definition 2:
Division ratio – (input frequency to output
frequency).
= (Number loaded + 8) x 2
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