參數(shù)資料
型號(hào): SP8121KS
元件分類: ADC
英文描述: 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO32
封裝: 0.300 INCH, PLASTIC, SOIC-32
文件頁數(shù): 12/13頁
文件大小: 168K
代理商: SP8121KS
SP8121DS/02
SP8121 Monolithic, 12-Bit Data Acquisition System
Copyright 2000 Sipex Corporation
8
R/C
STATUS
DB11 - DB0
tHRH
tC
DATA VALID
tHDR
tDDR
tDS
HIGH–Z
HIGH PULSE FOR R/C DYNAMIC CHARACTERISTICS
V
CC = +15V; VLOGIC = +5V; TA = 25°C
PARAMETER
MIN.
TYP.
MAX.
UNIT
CONDITIONS
t
HRH
High R/C Pulse Width
25
ns
t
DS
STATUS Delay from R/C
200
ns
t
C
Conversion Time
13
25
sT
MIN to TMAX
t
DDR
Data Access Time
150
ns
t
HDR
Data Valid after R/C Low
25
ns
Figure 5. High Pulse for R/C — Outputs Enabled While R/C is High, Otherwise High Impedance
Figure 6. Low Pulse for R/C
R/C
STATUS
DB11 - DB0
tHRL
tC
DATA VALID
tMDH
tDS
tHDR
tHS
MA0 - MA2
tMDS
LOW PULSE FOR R/C DYNAMIC CHARACTERISTICS
V
CC = +15V; VLOGIC = +5V; TA = 25°C
PARAMETER
MIN.
TYP.
MAX.
UNIT
CONDITIONS
t
HRL
Low R/C Pulse Width
50
ns
t
DS
Status Delay from R/C
200
ns
t
HDR
Data Valid after R/C
25
ns
t
HS
Status Delay after Data Valid 500
ns
t
MDS
MUX Data Setup
50
ns
t
MDH
MUX Data Valid
3
10
s
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