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參數(shù)資料
| 型號(hào)： | SP8121JS |
| 英文描述： | Monolithic, 12-Bit Data Acquisition System |
| 中文描述： | 單片，12位數(shù)據(jù)采集系統(tǒng) |
| 文件頁(yè)數(shù)： | 4/13頁(yè) |
| 文件大?。?/td> | 168K |
| 代理商： | SP8121JS |
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SP8121DS/02
SP8121 Monolithic, 12-Bit Data Acquisition System
4
Copyright 2000 Sipex Corporation
SP8121 PINOUT
1
16
2
3
4
5
6
7
8
9 10 11 12 13 14 15
17
23 22 21 20 19 18
24
30 29 28 27 26 25
32 31
D
D
D
D
D
D
D
D
D
D
D
D
M
M
M
L
V
L
S
R
C
V
C
O
G
A
A
A
A
A
A
A
A
A
CONTROL
LOGIC
C
12-BIT ADC
8-CHANNEL
MULTIPLEXER
DECODE
REF
S
SP8121 CONTROL TRUTH TABLE
CE
R/C
OPERATION
L->H
0
Start Conversion
1
0
Start Conversion
1
H ->L
Start Conversion
1
1
Enable 12-bit Output
(when STATUS=0)
SP8121 MULTIPLEXER TRUTH TABLE
LATCH MA
2
H -> L
H -> L
H -> L
H -> L
H -> L
H -> L
H -> L
H -> L
0
1
MA
1
0
0
1
1
0
0
1
1
X
X
MA
0
0
1
0
1
0
1
0
1
X
X
OPERATION
CH
O
Selected
CH
1
Selected
CH
2
Selected
CH
3
Selected
CH
4
Selected
CH
5
Selected
CH
6
Selected
CH
7
Selected
Prev. CH “n” Held
Prev. CH “n” Held
0
0
0
0
1
1
1
1
X
X
SP8121 PINOUT
STATUS — Identifies valid data output; goes to
logic high during conversion; goes to logic low
when conversion is completed and data is valid
R/C — Read/Convert — Initiates conversion on
the high-to-low transition; logic low discon-
nects data bus; logic high initiates read
CE — Chip Enable — Logic low disables read
or convert; logic high enables read or convert
LATCH — MUX Address Latch — Logic high
to low transition captures MUX address on
MUX address lines
MA
, MA
, MA
— MUX Address 0, 1 & 2 —
Selects analog input channels CH
0
through CH
7
DB
through DB
— Data Outputs — Logic
high is binary true; logic low binary false
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相關(guān)代理商/技術(shù)參數(shù) |
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