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| 型號： | SP774BKS |
| 元件分類： | ADC |
| 英文描述： | 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO28 |
| 封裝： | 0.300 INCH, SOIC-28 |
| 文件頁數(shù)： | 5/15頁 |
| 文件大小： | 150K |
| 代理商： | SP774BKS |
SP574B/674B/1674B/774B
12–Bit Sampling A/D Converters
Copyright 2000 Sipex Corporation
13
STAND–ALONE MODE TIMING CHARACTERISTICS
Typical @ 25C, V
CC= +15V or +12V, VLOGIC = +5V, VEE =0V, unless otherwise specified.
PARAMETER
MIN.
TYP .
MAX.
UNITS
CONDITIONS
tHRL Low R/C Pulse Width 2
50
ns
tDS
STS Delay from R/C 2
200
ns
tHDR Data Valid After R/C Low 2
25
ns
tHS
STS Delay After Data Valid 2
300
1000
ns
tHRH High R/C Pulse Width
150
ns
tDDR Data Access Time
150
ns
NOTES:
1.
Parameters guaranteed by design and sample tested.
2.
Parameters 100% tested @ 25C on special orders.
R/C
STS
DB11–DB0
tHRL
DATA VALID
tDS
DATA VALID
tC
tHS
tHDR
Figure 8. Low Pulse for R/C — Outputs Enabled After Conversion
Figure 9. High Pulse For R/C — Outputs Enabled While R/C is High, Otherwise High Impedance
R/C
STS
DB11–DB0
DATA VALID
tDS
tC
tHRH
HIGH–Z
tDDR
tHDR
OBSOLETE
-
HIST
ORICAL
REFERENCE
ONL
Y
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