參數(shù)資料
型號: SP7545KCN
廠商: SPECTRUM CONTROL INC
元件分類: DAC
英文描述: PARALLEL, WORD INPUT LOADING, 2 us SETTLING TIME, 12-BIT DAC, PDIP20
封裝: 0.300 INCH, PLASTIC, DIP-20
文件頁數(shù): 3/6頁
文件大?。?/td> 124K
代理商: SP7545KCN
SP7545
12–Bit, Buffered Multiplying DAC
Copyright 2000 Sipex Corporation
3
SPECIFICATIONS (continued)
(T
A=25°C; VDD =+5V, VREF = +10V; IO1 = AGND = GND = 0V; unipolar unless otherwise noted.)
PARAMETER
MIN.
TYP.
MAX.
UNIT
CONDITIONS
DIGITAL INPUTS
Logic Levels
V
IH
2.4
V
DD
Volts
V
DD = +5V
2.4
Volts
V
DD = +5V; Note 5
13.5
V
DD
Volts
V
DD = +15V
13.5
Volts
V
DD = +15V; Note 5
V
IL
-0.3
0.8
Volts
V
DD = +5V
0.8
Volts
V
DD = +5V; Note 5
-0.3
1.5
Volts
V
DD = +15V
1.5
Volts
V
DD = +15V; Note 5
Input Current
±1.0
AV
IN = 0V or VDD
±10
A
Note 5 and 9
Input Capacitance
V
IN = 0; Note 5 and 8
Bits 1—12
5
pF
WR, CS
20
pF
Coding
Unipolar
Binary
Bipolar
Offset Binary
POWER REQUIREMENTS
Supply Current
2.0
mA
All digital inputs V
IL or VIH
2.0
mA
Note 5; all digital inputs
V
IL or VIH
0.5
mA
Note 18
mA
Note 5 and 18
ENVIRONMENTAL AND MECHANICAL
Operating Temperature
Commercial
0
+70
°C
Industrial
-40
+85
°C
Storage Temperature
-65
+150
°C
Package
20–pin Plastic DIP
20–pin Plastic LCC
Notes and Cautions:
1.
Do not apply voltages higher than V
DD or less than GND potential on any terminal other than VREF or VRFB.
2.
The digital inputs are diode-clamp protected against ESD damage. However, permanent damage may
occur on unprotected units from high-energy electrostatic fields. Keep units in conductive foam at all
times until ready to use.
3.
Use proper anti-static handling procedures.
4.
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation at or above these specifications is not
implied. Exposure to the above maximum rated conditions for extended periods may affect device
reliability.
5.
From T
MIN to TMAX.
6.
End-point linearity
7.
Differential Non-linearity is the deviation of an output step from the theoretical value of 1 LSB for any two
adjacent digital input codes.
8.
Guaranteed by design, but not production tested.
9.
Logic inputs are MOS gates. I
IN typically is less than 1nA @ 25°C.
10.
AC performance characteristics are included for design guidance only and are subject to sample testing
only.
11.
R
L = 100, CEXT = 13pF; all data inputs 0V to VDD or VDD to 0V; from 50% digital input change to 90% of
final analog output.
12.
Settling to
±0.01% FSR (strobed); all data inputs 0V to V
DD or VDD to 0V.
13.
V
REF = 0V, DAC register alternatively loaded with all 0’s and all 1’s.
14.
V
REF = 20VP-P; F = 10kHz sinewave.
15.
V
REF = 20VP-P; F = 1kHz sinewave.
16.
Measured using internal feedback resistor with DAC loaded with all 1’s.
17.
All digital inputs = 0V.
18.
All digital inputs 0V or V
DD.
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