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參數(shù)資料
| 型號： | SP708TEU |
| 英文描述： | +3.0V/+3.3V Low Power Microprocessor Supervisory Circuits |
| 中文描述： | 3.0V / 3.3V低功耗微處理器監(jiān)控電路 |
| 文件頁數(shù)： | 11/18頁 |
| 文件大?。?/td> | 213K |
| 代理商： | SP708TEU |
11
Rev. 10-17-00 SP706 +3.0/ +3.3 Low Power Microprocessor Circuits Copyright 2000 Sipex Corporation
To build an early-warning circuit for power
failure, connect the PFI pin to a voltage divider
as shown in
Figure 16
. Choose the voltage
divider ratio so that the voltage at PFI falls
below 1.25V just before the +5V regulator drops
out. Use PFO to interrupt the
μ
P so it can prepare
for an orderly power-down.
Manual Reset
The manual-reset input (MR) allows RESET to
be triggered by a pushbutton switch. The switch
is effectively debounced by the 140ms
minimum RESET pulse width. MR is TTL/
CMOS logic compatible, so it can be driven by
an external logic line. MR can be used to force
a watchdog timeout to generate a RESET pulse
in the SP706P/R/S/T-SP708R/S/T series.
Simply connect WDO to MR.
Figure 14. Watchdog Timing Waveforms
Figure 15. Timing Diagrams with WDI Tri-stated. The RESET Output is the Inverse of the RESET Waveform
Shown.
t
RS
RESET*
WDO
0V
WDI
RESET*
0V
+3.3V
0V
0V
t
WD
t
WD
t
WD
t
WP
* externally triggered LOW by MR,
RESET is for the SP813L/813M only
+3.3V
+3.3V
+3.3V
V
CC
RESET
0V
0V
0V
t
RS
t
RS
t
MR
0V
MR*
WDO
V
RT
V
RT
*externally driven LOW
t
MD
+3.3V
+3.3V
+3.3V
+3.3V
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