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參數(shù)資料
| 型號： | SP6340EK1-L-W-H-D |
| 元件分類： | 電源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO6 |
| 封裝： | LEAD FREE, MO-193AA, TSOT-6 |
| 文件頁數(shù)： | 28/32頁 |
| 文件大?。?/td> | 1342K |
| 代理商： | SP6340EK1-L-W-H-D |
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Date: 4/10/06 Rev J
SP6340 - SP6342 Dual Power Supervisory Circuit
Copyright 2006 Sipex Corporation
5
PIN DESCRIPTION
Pin #
Name
Description
1V1
First supply voltage input. Also powers internal circuitry. Trip
threshold voltage internally set.
2V2
Second supply voltage input. Trip threshold voltage internally set.
3
WDI
Watch-Dog Input pin. When no transition is detected at the WDI pin
for the duration of WDI timeout period, reset is asserted. WDOB
remains at “LOW” logic level after watchdog timeout period is
expired and it remains “LOW” until WDI makes a transition.
RST/RSTB output is not affected by the watchdog functionality in the
parts with separate WDOB output. The watchdog timer clears
whenever the reset is asserted or a transition is observed at WDI pin.
4
WDOB
Watch Dog Output. Open-Drain or CMOS, active LOW. If WDI
remains at “HIGH” or “LOW” logic level for longer than the
watchdog timeout period, the internal watchdog timer overflows and
WDOB is asserted. WDOB does not de-assert until the watchdog is
cleared via transition at the WDI pin. Another scenario for WDOB to
assert is when the reset output is asserted due to an under-voltage
V1 or V2 condition. WDO de-asserts without a reset timeout period.
Floating WDI will not disable watchdog timer in devices with
dedicated WDOB output. Open-drain WDOB outputs require an
external pull-up resistor. CMOS outputs are referenced to V1.
5
GND
Common ground reference pin.
6
RSTB
Reset output. Open-Drain or CMOS, active high or low. Reset is
asserted when any of the supply inputs is below its trip threshold. It
stays asserted for 200 ms (typical / default) after the last supply input
traverses its trip threshold. Reset is guaranteed to be in the correct
state for V1>0.9V. RSTB asserts when V1 or V2 drop below their
corresponding reset thresholds. RSTB remains asserted for the
reset timeout period after V1 and V2 exceed their corresponding
reset thresholds. Open-drain outputs require an external pull-up
resistor. CMOS outputs are referenced to V1.
相關PDF資料 |
PDF描述 |
|---|---|
| SP6340EK1-L-W-J-A/TR | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO6 |
| SP6340EK1-L-X-E-B/TR | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO6 |
| SP6340EK1-L-X-H-D | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO6 |
| SP6340EK1-L-X-J-A/TR | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO6 |
| SP6340EK1-L-Y-A-A/TR | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO6 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| SP6341 | 制造商:SIPEX 制造商全稱:Sipex Corporation 功能描述:Triple レPower Supervisory Circuit with Manual Reset and Watchdog |
| SP6342EK1-L/TR | 功能描述:監(jiān)控電路 Dual Pwr w/Watchdog RoHS:否 制造商:STMicroelectronics 監(jiān)測電壓數(shù): 監(jiān)測電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復位:Resettable 監(jiān)視器:No Watchdog 電池備用開關:No Backup 上電復位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
| SP64/1.2/BLUE | 制造商:Farnell / Pro-Power 功能描述:HEATSHRINK 6.4MM BLUE 1.2M 制造商:pro-power 功能描述:HEATSHRINK, 6.4MM, BLUE, 1.2M 制造商:pro-power 功能描述:HEATSHRINK, 6.4MM, BLUE, 1.2M; I.D. Supplied - Metric:6.4mm; I.D. Supplied - Imperial:0.251"; I.D. Recovered Max - Metric:3.2mm; I.D. Recovered Max - Imperial:0.125"; Shrink Ratio:2:1; Shrink Tubing / Boot Material:PO (Polyolefin); ;RoHS Compliant: Yes |
| SP64/1.2/BLUE | 制造商:Farnell / Pro-Power 功能描述:HEAT SHRINK 6.4MM BLUE 1.2M |
| SP64/1.2/BROWN | 制造商:Farnell / Pro-Power 功能描述:HEAT SHRINK 6.4MM BROWN 1.2M |
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