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參數(shù)資料
| 型號(hào)： | SP6330EK1-L-X-D-A |
| 元件分類： | 電源管理 |
| 英文描述： | 4-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO8 |
| 封裝： | LEAD FREE, MO-193BA, TSOT-8 |
| 文件頁數(shù)： | 29/33頁 |
| 文件大?。?/td> | 1632K |
| 代理商： | SP6330EK1-L-X-D-A |
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Nov20-06 Rev M
SP6330/32/34 Quad Power Supervisory Circuit Family
Copyright 2006 Sipex Corporation
5
PIN DESCRIPTION
Pin #
Name
Description
1
V1
First supply voltage input. Also powers internal circuitry. Trip threshold
voltage internally set.
2
V2
Second supply voltage input. Trip threshold voltage internally set.
3
MRIB
Manual Reset Input pin. Active low. It has an internal pull-up resistor.
Reset asserted when MRIB is pulled low and is kept asserted for
200ms after MRIB is released or pulled high. Leave open if not used.
4
V3
Input for the third supply voltage. Trip threshold is 0.5V.
5
V4
Input for the fourth supply voltage. Trip threshold is 0.5V.
6
GND
Common ground reference pin.
7
WDI
Watch-Dog Input pin. When no transition is detected at the WDI pin for
the duration of WDI timeout period, reset is asserted. Leave open if
not used. RST/RSTB output is used to signal watchdog timeout
overflow. RST/RSTB output pulses high/low (depending on the active
reset polarity) for the reset timeout period after each watchdog timeout
overflow. The watchdog timer clears whenever the reset is asserted
or manual reset is asserted or a transition is observed at WDI pin.
Watchdog timer functionality can be disabled in parts by leaving this
input floating.
8
RST/RSTB
Reset output. Open-Drain or CMOS, active high or low. Reset is
asserted when any of the four supply inputs is below its trip threshold.
It stays asserted for 200 ms (typical / default) after the last supply input
traverses its trip threshold. Reset is guaranteed to be in the correct
state for V1>0.9V. RST/RSTB asserts when V1 or V2 or V3 or V4 drop
below their corresponding reset thresholds, or MRIB is pulled
“LOW” or the watchdog timer triggers a reset (devices without
WDOB). RST/RSTB remains asserted for the reset timeout period
after V1 and V2 and V3 and V4 exceed their corresponding reset
thresholds or MRIB goes “LOW” to “HIGH”.
Open-drain outputs
require an external pull-up resistor. CMOS outputs are referenced to
V1.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SP6330EK1-L-X-J-C | 功能描述:監(jiān)控電路 Quad microPower 監(jiān)控電路 RoHS:否 制造商:STMicroelectronics 監(jiān)測(cè)電壓數(shù): 監(jiān)測(cè)電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開關(guān):No Backup 上電復(fù)位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
| SP6330EK1-L-X-J-C/TR | 功能描述:監(jiān)控電路 Quad Micropower w/ Manual Reset&Watchdg RoHS:否 制造商:STMicroelectronics 監(jiān)測(cè)電壓數(shù): 監(jiān)測(cè)電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開關(guān):No Backup 上電復(fù)位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
| SP6330EK1-L-Z-J-C | 功能描述:監(jiān)控電路 Quad microPower 監(jiān)控電路 RoHS:否 制造商:STMicroelectronics 監(jiān)測(cè)電壓數(shù): 監(jiān)測(cè)電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開關(guān):No Backup 上電復(fù)位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
| SP6330EK1-L-Z-J-C/TR | 功能描述:監(jiān)控電路 Quad Micropower w/ Manual Reset&Watchdg RoHS:否 制造商:STMicroelectronics 監(jiān)測(cè)電壓數(shù): 監(jiān)測(cè)電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開關(guān):No Backup 上電復(fù)位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
| SP6332 | 制造商:SIPEX 制造商全稱:Sipex Corporation 功能描述:Quad レPower Supervisory Circuits with Manual Reset & Watchdog |
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