參數(shù)資料
型號: SP6330EK1-L-S-H-A
元件分類: 電源管理
英文描述: 4-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO8
封裝: LEAD FREE, MO-193BA, TSOT-8
文件頁數(shù): 28/33頁
文件大?。?/td> 1632K
代理商: SP6330EK1-L-S-H-A
Nov20-06 Rev M
SP6330/32/34 Quad Power Supervisory Circuit Family
Copyright 2006 Sipex Corporation
4
ELECTRICAL CHARACTERISTICS
PARAMETER
MIN
TYP
MAX
UNITS
CONDITIONS
V3 Input Threshold
490
500
510
mV
V3 Input Current
-50
50
nA
TA = +25C
V3 Threshold
Hysteresis
1.5
mV
V4 Input Threshold
490
500
510
mV
V4 Input Current
-50
50
nA
TA = +25C
V4 Threshold
Hysteresis
1.5
mV
MRIB Input
Threshold
0.2*V1
V
Vil
MRIB Input
Threshold
0.8*V1
V
Vih
MRIB Minimum
Input Pulse Width
1
us
MRIB Glitch
Rejection
150
ns
MRIB to RST/RSTB
Delay
100
ns
MRIB Pull-Up
Resistance
30
55
85
k
Watchdog Timeout
Period
1.3
1.6
1.9
sec
WDI Pulse Width
0.1
us
WDI Input
Threshold
0.2*V1
V
Vil
WDI Input
Threshold
0.8*V1
V
Vih
WDI Input Current
-500
500
nA
WDI = 0.0V or V1
RSTB
(CMOS or OD)
0.2*V1
V
V1 = Vth1 - 0.1V, Isink = 1mA,
output asserted
RSTB (CMOS)
0.8*V1
V
V1 = Vth1 + 0.1V, Isource =
1mA, output not asserted
RST (CMOS)
0.8*V1
V
V1 = Vth1 - 0.1V, Isource =
1mA, output asserted
RST (CMOS)
0.2*V1
V
V1 = Vth1 + 0.1V, V2 > Vth2,
V3 > 0.5, V4 > 0.5, Isource =
1mA, output not asserted
RSTB Output OD
Leakage Current
2
nA
TA = +25C
V3 RESET COMPARATOR INPUT
V4 RESET COMPARATOR INPUT
MRIB - MANUAL RESET INPUT
V1 =1.6V to 5.5V; TA = -40C to +85C; unless otherwise noted. Typical values are at TA =+25C
RESET OUTPUTS RST / RSTB
WDI - WATCHDOG INPUT
相關(guān)PDF資料
PDF描述
SP6330EK1-L-T-E-B 4-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO8
SP6330EK1-L-T-G-A/TR 4-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO8
SP6330EK1-L-U-E-D 4-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO8
SP6330EK1-L-U-J-C 4-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO8
SP6330EK1-L-V-H-D/TR 4-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO8
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