參數(shù)資料
型號: SP6120HVCY
英文描述: CAPACITOR, F/TERM 6800PF 50V X8R 0805CAPACITOR, F/TERM 6800PF 50V X8R 0805; CAPACITANCE:6.8NF; VOLTAGE RATING, DC:50V; CAPACITOR DIELECTRIC TYPE:CERAMIC MULTI-LAYER; SERIES:08055F; TOLERANCE, :10%; TOLERANCE, -:10%; TEMP, OP. RoHS Compliant: Yes
中文描述: 高電壓,同步,降壓控制器適合2A至20A條,高性能,DC - DC電源轉(zhuǎn)換器
文件頁數(shù): 18/22頁
文件大小: 308K
代理商: SP6120HVCY
18
Date: 5/25/04
SP6120 Low Voltage, AnyFET
TM
, Synchronous, Buck Controller Copyright 2004 Sipex Corporation
Current Sense
The SP6120 allows sensing current using the
inductor, PCB trace or current-sense resistor.
Inductor-sense utilizes the voltage drop across
the ESR of the inductor, while PCB trace and
current-sense resistor introduce additional re-
sistance in series with the inductor. The resis-
tance of the sense element determines the
overcurrent protection threshold as follows,
I
LIM
= 43mV
R
SEN
R
SEN
= current-sense resistance which can be
implemented as ESR of the inductor, trace or
discrete resistor.
The maximum power dissipation on the current-
sense element is:
I
P
=
For the inductor-sense scheme shown in the
application circuit, R
S
and C
S
are used to repli-
cate the signal across the ESR of the inductor. R
S
and C
S
can be looked at as a low pass filter
whose output represents the DC differential
voltage between the switch node and the output.
At steady state, this voltage happens to be the
output current times the ESR of the inductor. In
addition, if the following relationship is satisfied,
L = R
S
C
S
ESR
the output of the RsCs filter represents the exact
voltage across the ESR, including the ripple.
Since the SP6120’s hiccup overcurrent protec-
tion scheme is intended to safeguard sustained
overload conditions, the DC portion of the cur-
rent signal is more of interest. Therefore, design-
ing the R
S
C
S
time constant higher than L/ESR
provides reliable current sense against any pre-
mature triggering due to noise or any transient
conditions. Pick Rs between 10k and 100k, and
Cs can be determined by:
SEN
OUT
SEN
R
2
(max)
C
S
= 2
L
1
ESR R
S
Here the time constant of R
S
C
S
is twice the value
of L/ESR.
In Figure 18, R1 and C1 provides a zero f
Z1
which needs to be placed at or below f
P(LC)
. If f
Z1
is made equal to f
P(LC)
for convenience, the
value of C1 can be calculated as
C
1
=
1
2
π
f
P(LC)
R
1
The optional C2 generates a pole f
P1
with R1 to
cut down high frequency noise for reliable op-
eration. This pole should be placed one decade
higher than the crossover frequency to avoid
erosion of phase margin. Therefore, the value of
the C2 can be derived from
C
2
=
1
20
π
f
CO
R
1
Figure 19 illustrates the overall loop frequency
response and frequency of each pole and zero.
To fine-tune the compensation, it is necessary to
physically measure the frequency response us-
ing a network analyzer.
Gain
-20db/dec
-40db/dec
-20db/dec
-20db/dec
-20db/dec
Error Amplifier
Loop
f
f
f
Z1
f
P(LC)
f
Z(ESR)
f
CO
f
P1
Figure 19. Frequency response of a stable system and its
error amplifier.
APPLICATIONS INFORMATION: Continued
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