參數(shù)資料
型號: SP6120B
英文描述: Low Voltage, AnyFETTM, Synchronous ,Buck Controller Ideal for 2A to 10A, High Performance, DC-DC Power Converters
中文描述: 低電壓,AnyFETTM,同步,降壓控制器適合2A至10A條,高性能,DC - DC電源轉(zhuǎn)換器
文件頁數(shù): 8/22頁
文件大小: 304K
代理商: SP6120B
8
Date: 5/25/04
SP6120B Low Voltage, AnyFET
TM
, Synchronous, Buck Controller Copyright 2004 Sipex Corporation
Figure 14. V
CC
Start Threshold vs. Temperature
Figure 15. V
CC
Stop Threshold vs. Temperature
Figure 16. Oscillator Frequency vs. Temperature
Figure 17. Oscillator Frequency vs. R
OSC
with V
CC
= 5V
and CGH = CGL = Open.
2.900
-40
-15
10
35
60
85
V
C
Temperature (
°
C)
2.875
2.850
2.825
2.800
2.850
-40
-15
10
35
60
85
V
C
Temperature (
°
C)
2.825
2.800
2.775
2.750
302
-40
-15
10
35
60
85
F
Temperature (
°
C)
301
300
299
298
200
300
400
500
600
700
800
5
10
15
20
25
30
F
R
OSC
(k
)
Typical Performance Characteristics
Unless otherwise specified: V
CC
= BST = ENABLE = 3.3V, R
OSC
= 18.7k, C
COMP
= 0.1
μ
F, C
SS
= 0.1
μ
F, CGH = CGL = 3.3nF, V
FB
= 1.25V,
ISP = ISN = 1.25V, SWN = GND = PGND = 0V, T
AMB
= 25
°
C.
THEORY OF OPERATION
General Overview
The SP6120B is a constant frequency, voltage
mode PWM controller for low voltage, DC/DC
step down converters. It has a main loop where
an external resistor (R
OSC
) sets the frequency and
the driver is controlled by the comparison of an
error amp output (COMP) and a 1V ramp signal.
The error amp has a transconductance of 600
μ
S,
an output impedance of 3 M
, an internal pole at
2 MHz and a 1.25V reference input. Although
the main control loop is capable of 0% and 100%
duty cycle, its response time is limited by the
external component selection. Therefore, a sec-
ondary loop, including a window comparator
positioned 3% above and below the reference,
has been added to insure fast response to line and
load transients. A unique “Ripple & Frequency
Independent” algorithm, added to the secondary
loop, insures that the window comparator does
not interfere with the main loop during normal
operation. In addition to receiving driver com-
mands from the main and secondary loops, the
Driver Logic is also controlled by the Program-
ming Logic, Fault Logic and Zero Crossing
Comparator. The Programming Logic tells the
Driver Logic whether the controller is using a
PFET or NFET high side driver as well as whether
the controller is operating in continuous or dis-
continuous mode. The Fault Logic holds the high
and low side drivers off if V
CC
dips below 2.75V,
if an over current condition exists, or if the part
is disabled through the ENABLE pin. The Zero
Crossing Comparator turns the lower driver off
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