
10
Rev. 2/15/01
SP6120 Low Voltage, AnyFET
TM
, Synchronous, Buck Controller Copyright 2001 Sipex Corporation
P
The NFET/PFET programmability is for the
high side MOSFET. When designing DC/DC
converters, it is not always obvious when to use
an NFET with a charge pump or a simple PFET
for the high side MOSFET. Often, the controller
has to be changed, making performance evalua-
tions difficult. This difficulty is worsened by the
limited availability of true low voltage control-
lers. In addition, by also programming the
mode, continuous or discontinuous, switch mode
power designs that are successful in bus applica-
tions can now find homes in portable applica-
tions.
Secondary Loop (3% Window Comparator)
DSP, microcontroller and microprocessor appli-
cations have very strict supply voltage require-
ments. In addition, the current requirements to
these devices can change drastically. Linear
regulators, typically the workhorse for DC/DC
step-down, do a great job managing accuracy
and transient response at the expense of effi-
ciency. On the other hand, PWM switching
regulators typically do a great job managing
efficiency at the expense of output ripple and
line/load step response. The trick in PWM
controller design is to emulate the transient
response of the linear regulator.
Of course improving transient response should
be transparent to the power supply designer.
Very often this is not the case. Usually the very
circuitry that improves the controllers transient
response adversely interferes with the main PWM
loop or complicates the board level design of the
power converter.
The SP6120 handles line/load transient response
in a new way. First, a window comparator
detects whether the output voltage is above or
below the regulated value by 3%. Then, a
proprietary “Ripple & Frequency Independent”
algorithm synchronizes the output of the win-
dow comparator with the peak and valley of the
inductor current waveform. 3% low detection is
synchronized with inductor current peak; 3%
high detection is synchronized with the inductor
current valley. However, in order to eliminate
any additional loops, the current peak and valley
are determined by the edges associated with the
on-time in the main loop. The set pulse corre-
sponding to the start of an on-time indicates a
current valley and the reset pulse corresponding
to the end of an on-time indicates a current peak.
In effect, the main loop determines the status of
the secondary loop.
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DC Load
MIN
0A
Output
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Reset
Set
V(V
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Main Loop
3% High
0V
V(V
CC
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3% Low
.
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TIME