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參數(shù)資料
| 型號： | SP5848KGQP1S |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | 2.2/1.3GHz 3-Wire Bus Dual Low Phase Noise PLL |
| 中文描述： | 2.2/1.3GHz 3線總線雙低相位噪聲鎖相環(huán) |
| 文件頁數(shù)： | 4/9頁 |
| 文件大小： | 67K |
| 代理商： | SP5848KGQP1S |
4
SP5848
Preliminary Information
Absolute maximum Ratings
All voltages referred to Vee at 0V
Characteristic
Value
Max
7
2.5
2.5
Vcc+0.3
+125
150
Conditions
Min
-0.3
Units
V
Vp-p
Vp-p
V
°
C
°
C
Supply voltages
RF1 input voltage
RF2 input voltage
All I/O ports DC offset
Storage temperature
Junction temperature
Package thermal resistance
chip to ambient
chip to case
Power consumption with all
Vcc =5.5V
ESD protection
Differential
Differential
-0.3
-55
100
30
121
°
C/W
°
C/W
mW
All ports off
2
kV
Mil std 883 latest revision methood 3015
class 1
Functional Description
The SP5848 contains two PLL frequency synthesiser
loops, each independently programmable from a 3-wire
bus. The device is optimised for application in double
conversion tuners where synthesiser 1 would form part
of the upconverter and synthesiser 2 part of the down
converter. Both loops are optimised for application in low
phase noise loops and furtherly synthesiser 2 offers low
comparison frequencies. A block diagram is contained in
Figure 1.
The device is programmed via a 3-wire bus where data
is fed on serial data and clock lines and is gated by an
enable line. Figure 3 indicates the format of the data.
The sequence and timing of data load is described below
in ‘programming mode’ description. Each synthesiser is
independently addressable and is defined by the LSB bit
within the data transmission.
A common reference frequency source and reference
divider is used to derive the comparison frequency for
both PLL loops. The reference division ratio is
programmable via the data bus as defined in Tables1
and 2.
The charge pump current for each loop is also
programmable via the data bus as defined in Tables 3
and 4
Two switching ports are provided to control switching
functions within the tuner. These ports also access test
signals within the PLL as defined in Figure 7. Ports
power up in high impedance state.
Programming Mode
The SP5848 is designed to be programmed from a
standard 3-wire bus consisting of clock, data and enable,
where the serial clock and data lines can be shared with
other devices and the enable line is a unique line for
individual device selection. To simplify programming
each synthesiser is independently addressed, with the
required loop being selected by the LSB bit , which
functions as the address, therefore to fully program the
device two complete data transmissions must be sent.
The data format for each transmission is contained in
Figure 3.
Test modes as described in Figure 7, can be invoked by
setting bit T0 in synthesiser 2 data word to a ‘1’ and
sending control data for bits T1-T2. In normal operation
where T0 is set to a ‘0’ bits T1 and T2 do not need to be
transmitted
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SP5848 | 2.2/1.3GHz 3-Wire Bus Dual Low Phase Noise PLL |
| SP5848KG | 2.2/1.3GHz 3-Wire Bus Dual Low Phase Noise PLL |
| SP5848QP1T | 2.2/1.3GHz 3-Wire Bus Dual Low Phase Noise PLL |
| SP8400 | Very Low Phase Noise Synthesiser Divider |
| SP8400KGMPES | Very Low Phase Noise Synthesiser Divider |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SP5848QP1T | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:2.2/1.3GHz 3-Wire Bus Dual Low Phase Noise PLL |
| SP585 | 制造商:Power-One 功能描述: |
| SP5875P/F | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SP5875P/F 是一顆電流模式PWM 控制芯片，內(nèi)建高壓電流源，在啟動階段提供啟動電流，由此可以構(gòu)建一個低損耗的啟動電路。適用于60W以內(nèi)的方案。SP5875P/F 的CS 腳設置有前沿消隱功能，并且內(nèi)置斜坡補償，結(jié)合多種工作模式，方便構(gòu)建高效率、低成本的AC/DC 應用方案。 |
| SP5876 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SP5876機功耗高性能離線反激PWM控制器 |
| SP58A | 制造商:Bogen Communications 功能描述:PAGING HORN 7.5 WATT 8 OHM |
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