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參數資料
| 型號： | SP5769AKGQP1T |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | 3GHz I2C Bus Synthesiser |
| 中文描述： | 3GHz的I2C總線合成器 |
| 文件頁數： | 3/11頁 |
| 文件大小： | 223K |
| 代理商： | SP5769AKGQP1T |
3
SP5769
Electrical Characteristics (continued)
2
3
0
Characteristic
V
PORT
= 0
·
7V
V
PORT
= V
CC
See Note 1
See Table 3
V
IN
= V
CC
V
IN
= V
EE
See Note 3
5V I
2
C logic level selected or open circuit
3
·
3V I
2
C logic level selected
V
IN
= V
EE
to V
CC
Conditions
Max.
Min.
Value
Units
mA
μ
A
mA
μ
A
V
V
μ
A
Typ.
10
1
2
0
·
5
1
·
5
10
Output Ports P3 - P0
Sink current
Leakage current
Address select
Input high current
Input low current
Logic level select
Input high level
Input low level
Input current
Pin
6-9
10
6
NOTES
1. Output ports high impedance on power-up, with SDA and SCL at logic
‘
0
’
.
2. If the REF/COMP output is not used, the output should be left open circuit or connected to V
CC
and disabled by setting RE =
‘
0
’
.
3. Bi-dectional port. When used as an output, the input logic state is ignored. When used as an input, the port should be switched into
high impedance (off) state.
Functional Description
The SP5769 contains all the elements necessary, with the
exception of a frequency reference, loop filter and external
high voltage transistor, to control a varactor tuned local
oscillator, so forming a complete PLL frequency
synthesised source. The device allows for operation with
a high comparison frequency and is fabricated in high
speed logic, which enables the generation of a loop with
good phase noise performance.
The RF input signal is fed to an internal preamplifier, which
provides gain and reverse isolation from the divider signals.
The output of the preamplifier interfaces with the 15-bit
fully programmable divider which is of MN
1
A architecture,
where the dual modulus prescaler is
4
16/17, the A counter
is 4 bits, and the M counter is 11 bits.
The output of the programmable divider is applied to the
phase comparator where it is compared in both phase and
frequency domains with the comparison frequency. This
frequency is derived either from the on-chip crystal
controlled oscillator or from an external reference source.
In both cases the reference frequency is divided down to
the comparison frequency by the reference divider which
is programmable into 1 of 16 ratios as detailed inTable 1.
The output of the phase detector feeds a charge pump
and loop amplifier section, which when used with an
external high voltage transistor and loop filter, integrates
the current pulses into the varactor line voltage. The
programmable divider output f
PD
/2 can be switched to port
P0 by programming the device into test mode. The test
modes are described inTable 5.
Programming
The SP5769 is controlled by an I
2
C data bus and is
compatible with both standard and fast mode formats and
with I
2
C data generated from nominal 3
·
3V and 5V sources.
The I
2
C logic level is selected by the bi-directional port
P3/ LOGLEV. 5V logic levels are selected by connecting
P3/ LOGLEV to V
CC
or leaving it open circuit; 3
·
3V logic
levels are set by connecting P3/LOGLEV to ground. If this
port is used as an input the P3 data should be programmed
to high impedance. If used as an output only 5V logic levels
can be used, in which case the logic state imposed by the
port on the input is ignored.
Data and clock are fed in on the SDA and SCL lines
respectively as defined by I
2
C bus format . The synthesiser
can either accept data (write mode), or send data (read
mode). The LSB of the address byte (R/W) sets the device
into write mode if it is low, and read mode if it is high.
Tables 2 and 3 illustrate the format of the data. The device
can be programmed to respond to several addresses,
which enables the use of more than one synthesiser in an
I
2
C bus system. Table 4 shows how the address is selected
by applying a voltage to the address input. When the device
receives a valid address byte, it pulls the SDA line low
during the acknowledge period, and during following
acknowledge periods after further data bytes are received.
When the device is programmed into read mode, the
controller accepting the data must be pulled low during all
status byte acknowledge periods to read another status
byte. If the controller fails to pull the SDA line low during
this period, the device generates an internal STOP
condition, which inhibits further reading.
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