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參數(shù)資料
| 型號： | SP5669KGMP1T |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | 2.7GHz I2C Bus Controlled Synthesiser |
| 中文描述： | 2.7GHz的I2C總線控制合成器 |
| 文件頁數(shù)： | 5/15頁 |
| 文件大?。?/td> | 237K |
| 代理商： | SP5669KGMP1T |
5
SP5669
Functional Description
The SP5669 contains all the elements necessary, with the
exception of a frequency reference, loop filter and external
high voltage transistor, to control a varicap tuned local
oscillator, so forming a complete PLL frequency
synthesised source. The device allows for operation with
a high comparison frequency and is fabricated in high
speed logic, which enables the generation of a loop with
good phase noise performance. The block diagram is
shown in Fig. 2.
The RF input signal is fed to an internal preamplifier, which
provides gain and reverse isolation from the divider
signals. The output of the preamplifier interfaces with the
17–bit fully programmable divider via a divide–by–two
prescaler. For applications up to 2GHz RF input, the
prescaler may be disabled so eliminating the degradation
in phase noise due to prescaler action. The divider is of
MN+A architecture, where the dual modulus prescaler is
16/17, the A counter is 4–bits, and the M counter is 13–bits.
The output of the programmable divider is fed to the phase
comparator where it is compared in both phase and
frequency domain with the comparison frequency. This
frequency is derived either from the on–board crystal
controlled oscillator or from an external reference source.
In both cases the reference frequency is divided down to
the comparison frequency by the reference divider which
is programmable into 1 of 15 ratios as detailed in Fig. 3.
The output of the phase detector feeds a charge pump and
loop amplifier section, which when used with an external
voltage transistor and loop filter, integrates the current
pulses into the varactor line voltage. By invoking the
device test modes as described in Fig. 5, the varactor drive
output can be disabled so switching the external transistor
’off’ and allowing an external voltage to be written to the
varactor line for tuner alignment purposes. Similarly, the
charge pump may be also disabled to a high impedance
state.
The programmable divider output Fpd/2 can be switched
to port P0 by programming the device into test mode. The
test modes are described in Fig. 5 high
Programming
The SP5669 is controlled by an I
2
C data bus. Data
and Clock are fed in on the SDA and SCL lines
respectively as defined by I
2
C bus format. The
synthesiser can either accept data (write mode) or
send data (read mode). The LSB of the address byte
(R/W) sets the device into write mode if it is low, and
read mode if it is high. Tables 1 and 2 in Fig. 4 illustrate
the format of the data. The device can be
programmed to respond to several addresses, which
enables the use of more than one synthesiser in an
I
2
C bus system. Table 3 in Fig.4 shows how the
address is selected by applying a voltage to the
’address’ input. When the device receives a valid
address byte, it pulls the SDA line low during the
acknowledge period, and during following
acknowledge periods after further data bytes are
received. When the device is programmed into read
mode, the controller accepting the data must pull the
SDA line low during all status byte acknowledge
periods to read another status byte. If the controller
fails to pull the SDA line low during this period, the
device generates an internal STOP condition, which
inhibits further reading.
Write Mode
With reference to Table 1, bytes 2 and 3 contain
frequency information bits 2 14 –2 0 inclusive.
Auxillary frequency bits 2 16 –2 15 are in byte 4. For
most frequencies only bytes 2 and 3 will be required.
The remainder of byte 4 and byte 5 control the
prescaler enable, reference divider ratio (see Fig. 3),
charge pump, REF/COMP output (see Fig. 5), output
ports and test modes (see Fig. 5).
After reception and acknowledgement of a correct
address (byte 1), the first bit of the following byte
determines whether the byte is interpreted as a byte
2 or 4, a logic ’0’ indicating byte 2 and a logic ’1’
indicating byte 4. Having interpreted this byte as
either byte 2 or 4 the following data byte will be
interpreted as byte 3 or 5 respectively. Having
received two complete data bytes, additional data
bytes can be entered, where byte interpretation
follows the same procedure, without readdressing
the device. This procedure continues until a STOP
condition is received. The STOP condition can be
generated after any data byte, if however it occurs
during a byte transmission, the previous data is
retained.
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