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| 型號： | SP509CF-L |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 15/29頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TXRX MULTIPROTOCOL 100LQFP |
| 產(chǎn)品變化通告： | SP509(C,E)F-L Discontinuation 01/Mar/2012 |
| 標準包裝： | 90 |
| 類型： | 收發(fā)器 |
| 驅(qū)動器/接收器數(shù)： | 8/8 |
| 規(guī)程： | 多協(xié)議 |
| 電源電壓： | 5V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-LQFP |
| 供應商設備封裝： | 100-LQFP（14x14） |
| 包裝： | 托盤 |
| 其它名稱： | 1016-1442 SP509CF-L-ND |
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ExarCorporation48720KatoRoad,FremontCA,9453850-668-707www.exar.comSP509_00_06080
Thisresistorisinvokedwhenthereceiveris
operatingasaV.receiver,inmodesEIA-
530,EIA-530A,RS-449/V.36,andX.2.The
samereceiversalsoincorporateatermina-
tionnetworkinternallyforV.35applications.
ForV.35,thereceiverinputterminationisa
“Y” termination consisting of two 51 resis-
tors connected in series and a 124 resistor
connected between the two 50 resistors
and V35RGND output. The V35RGND is
usually grounded. The receiver itself is
identicaltotheV.receiver.
The differential receivers can be configured
to be ITU-T-V.0 single-ended receivers
by internally connecting the non-inverting
input to ground. This is internally done
by default from the decoder. The non-in-
verting input is rerouted to V0GND and
can be grounded separately. The ITU-T-
V.0 receivers can operate over Mbps
and are used in RS-449/V.36, EA-530,
EA-530AandX.2modesasCategoryII
signalsasindicatedbytheircorresponding
specifications. All receivers include an en-
able/disablelinefordisablingthereceiver
output allowing convenient half-duplex
configurations. The enable pins will either
enableordisabletheoutputofthereceivers
accordingtotheappropriateactivelogicil-
lustratedonFigure47.Thereceiver’senable
linesincludeaninternalpull-uporpull-down
device,dependingontheactivepolarityof
thereceiver,thatenablesthereceiverupon
power up if the enable lines are left floating.
During disabled conditions, the receiver
outputswillbeatahighimpedancestate.
If the receiver is disabled any associated
termination is also disconnected from the
inputs.
Allreceiversincludeafail-safefeaturethat
outputsalogichighwhenthereceiverinputs
areopen,terminatedbutopen,orshorted
together. For single-ended V.28 and V.0
receivers, there are internal 5k pull-down
resistors on the inputs which produces a
logichigh(“”)atthereceiveroutputs.The
differentialreceivershaveaproprietarycir-
cuitthatdetectopenorshortedinputsand
ifso,willproducealogicHIGH(“”)atthe
receiveroutput.
ChARGEPUMP
ThechargepumpisaExar-patenteddesign
(5,306,954) and uses a unique approach
compared to older less-efficient designs.
Thechargepumpstillrequiresfourexternal
capacitors, but uses four-phase voltage
shifting technique to attain symmetrical
powersupplies.ThechargepumpV
DDand
V
SS outputs are regulated to +5.8V and
-5.8V,respectively.Thereisafree-running
oscillator that controls the four phases of
thevoltageshifting.Adescriptionofeach
phasefollows.
Phase1
__V
SSchargestorage——Duringthisphase
oftheclockcycle,thepositivesideofcapaci-
torsC
andC2areinitiallychargedtoVCC.C+
isthenswitchedtogroundandthecharge
inC
-istransferredtoC2-.SinceC2+iscon-
nectedtoV
CC,thevoltagepotentialacross
capacitorC
2isnow2XVCC.
Phase2
—V
SStransfer—Phasetwooftheclockcon-
nectsthenegativeterminalofC
2totheVSS
storagecapacitorandthepositiveterminal
ofC
2toground,andtransfersthenegative
generated voltage to C
3. This generated
voltage is regulated to –5.8V. Simultane-
ously,thepositivesideofthecapacitorC
isswitchedtoV
CCandthenegativesideis
connectedtoground.
Phase3
—V
DDchargestorage—Thethirdphaseof
the clock is identical to the first phase—the
chargetransferredinC
produces –VCC in
thenegativeterminalofC
whichisapplied
to the negative side of the capacitor C
2 .
Since C
2+ is at VCC, the voltage potential
acrossC
2is2XVCC.
Phase4
—V
DD transfer —The fourth phase of the
clockconnectsthenegativeterminalofC
2
toground,andtransfersthegenerated5.8V
acrossC
2toC4,theVDDstoragecapacitor.
This voltage is regulated to +5.8V.At the
regulatedvoltage,theinternaloscillatoris
disabledandsimultaneouslywiththis,the
positivesideofcapacitorC
isswitchedto
V
CC and the negative side is connected to
ground,andthecyclebeginsagain.
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