參數(shù)資料
型號(hào): SP331CT-L
廠商: Exar Corporation
文件頁(yè)數(shù): 12/13頁(yè)
文件大?。?/td> 0K
描述: IC TXRX RS232/485 PROG 28WSOIC
標(biāo)準(zhǔn)包裝: 27
類型: 收發(fā)器
驅(qū)動(dòng)器/接收器數(shù): 4/4
規(guī)程: RS232,RS485
電源電壓: 5V
安裝類型: 表面貼裝
封裝/外殼: 28-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 28-SOIC W
包裝: 管件
其它名稱: 1016-1133-5
8
Exar Corporation 48720 Kato Road, Fremont CA, 94538 50-668-707 www.exar.com
SP33_00_0260
FUNCTION TABLE FOR SELECT PINS
A
B
C
D
MODE
FUNCTION
0
RS-232
All four RS-232 drivers active
0
RS-232
All four RS-232 drivers tri-state
0
0
RS-232
All four RS-232 drivers tri-state
0
RS-232
RS-232 (4ch) Loopback
0
0
RS-232/RS-485
T and T2 active RS-232; T3 tri-state RS-485
0
0
RS-232/RS-485
T and T2 tri-state RS-232; T3 active RS-485
0
0
RS-232/RS-485
T and T2 active RS-232; T3 tri-state RS-485
0
RS-232/RS-485
RS-232 (2ch) / RS-485 (ch) Loopback
0
RS-485/RS-232
T active RS-485; T3 and T4 active RS-232
0
RS-485/RS-232
T tr-state RS-485; T3 active RS-232; T4 active RS232
0
0
RS-485/RS-232
All RS-485 and RS-232 drivers tri-state
0
RS-485/RS-232
RS-485 (ch) / RS-232 (2ch) Loopback
0
RS-485
T and T3 active RS-485
0
RS-485
T tri-state RS-485; T3 active RS-485
0
RS-485
T active RS-485; T3 tri-state RS-485
RS-485
RS-485 (2ch) Loopback
Table 1. Mode Function Table. (Refer to Control Logic Confirmations for Block Diagrams)
THEORY OF OPERATION
The
SP331 is made up of four separate
circuit blocks — the charge pump, drivers,
receivers, and decoder. Each of these circuit
blocks is described in more detail below.
Charge–Pump
Thechargepumpisa
Exar–patenteddesign
(U.S.5,306,954)andusesauniqueapproach
compared to older less efficient designs.
The charge pump still requires four external
capacitors, but uses a four–phase voltage
shifting technique to attain symmetrical 0V
power supplies. Figure 5(a) shows the
waveformfoundonthepositivesideofcapci-
tor C2, and Figure 5(b) shows the negative
side of capcitor C2. There is a free–running
oscillator that controls the four phases of
the voltage shifting. A description of each
phase follows.
Phase 1
— V
SS charge storage —During this phase of
the clock cycle, the positive side of capaci-
tors C
and C2 are initially charged to +5V.
C
l
+
is then switched to ground and charge
transferred to C
2
. Since C
2
+
is connected to
+5V, the voltage potential across capacitor
C
2 is now 0V.
Phase 2
— V
SS transfer — Phase two of the clock con-
nects the negative terminal of C
2 to the VSS
storage capacitor and the positive terminal
of C
2 to ground, and transfers the generated
–l0V to C
3. Simultaneously, the positive side
of capacitor C
is switched to +5V and the
negative side is connected to ground.
Phase 3
— V
DD charge storage — The third phase
of the clock is identical to the first phase
— the charge transferred in C
produces
–5V in the negative terminal of C
, which
is applied to the negative side of capacitor
C
2. Since C2
+
is at +5V, the voltage potential
across C
2 is l0V.
Phase 4
— V
DD transfer — The fourth phase of the
clock connects the negative terminal of C
2
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