參數資料
型號: SP3232E
英文描述: True +3.0V to +5.5V RS-232Transceivers(標準+3.0V 至 +5.5V RS-232收發(fā)器(2發(fā)2收))
中文描述: 真正的3.0V至5.5V的RS - 232Transceivers(標準3.0V至5.5V的RS - 232接口收發(fā)器(2發(fā)2收))
文件頁數: 10/19頁
文件大?。?/td> 174K
代理商: SP3232E
SP3222E/3232EDS/21 SP3222E/3232E True +3.0 to +5.0V RS-232 Transceivers
Copyright 2000 Sipex Corporation
10
Receivers
The receivers convert EIA/TIA-232 levels to
TTL or CMOS logic output levels. All receivers
have an inverting tri-state output. These receiver
outputs (RxOUT) are tri-stated when the enable
control EN = HIGH. In the shutdown mode, the
receivers can be active or inactive. EN has no
effect on TxOUT. The truth table logic of the
SP3222E/3232E
driver and receiver outputs can
be found in
Table 2
.
Since receiver input is usually from a transmis-
sion line where long cable lengths and system
interference can degrade the signal, the inputs
have a typical hysteresis margin of 300mV. This
ensures that the receiver is virtually immune to
noisy transmission lines. Should an input be left
unconnected, a 5k
pulldown resistor to ground
will commit the output of the receiver to a HIGH
state.
Charge Pump
The charge pump is a
Sipex
–patented design
(5,306,954) and uses a unique approach com-
pared to older less–efficient designs. The charge
pump still requires four external capacitors, but
uses a four–phase voltage shifting technique to
attain symmetrical 5.5V power supplies. The
internal power supply consists of a regulated
dual charge pump that provides output voltages
5.5V regardless of the input voltage (V
CC
) over
the +3.0V to +5.5V range.
In most circumstances, decoupling the power
supply can be achieved adequately using a 0.1
μ
F
bypass capacitor at C5 (refer to
Figures 6
and
7
).
In applications that are sensitive to power-sup-
ply noise, decouple V
to ground with a capaci-
tor of the same value as charge-pump capacitor
C1. Physically connect bypass capacitors as
close to the IC as possible.
The charge pumps operate in a discontinuous
mode using an internal oscillator. If the output
voltages are less than a magnitude of 5.5V, the
charge pumps are enabled. If the output voltage
exceed a magnitude of 5.5V, the charge pumps
are disabled. This oscillator controls the four
phases of the voltage shifting. A description of
each phase follows.
Phase 1
— V
charge storage — During this phase of
the clock cycle, the positive side of capacitors C
1
and C
are initially charged to V
. C
l
switched to GND and the charge in C
ferred to C
voltage potential across capacitor C
2
is now 2
times V
CC
.
+
is then
is trans-
. Since C
+
is connected to V
, the
Phase 2
— V
transfer — Phase two of the clock con-
nects the negative terminal of C
to the V
SS
storage capacitor and the positive terminal of C
2
to GND. This transfers a negative generated
voltage to C
. This generated voltage is regu-
lated to a minimum voltage of -5.5V. Simulta-
neous with the transfer of the voltage to C
, the
positive side of capacitor C
is switched to V
CC
and the negative side is connected to GND.
Phase 3
— V
charge storage — The third phase of the
clock is identical to the first phase — the charge
transferred in C
produces –V
in the negative
terminal of C
, which is applied to the negative
side of capacitor C
. Since C
voltage potential across C
2
is 2 times V
CC
.
+
is at V
CC
, the
Table 2. Truth Table Logic for Shutdown and Enable
Control
N
D
H
S
N
E
T
U
O
x
T
T
U
O
x
R
0
0
e
T
e
v
A
0
1
e
T
e
T
1
0
e
v
A
e
v
A
1
1
e
v
A
e
T
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