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參數(shù)資料
| 型號(hào)： | SP2209EEY-L |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 2/17頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TXRX RS232 DUAL PORT 38TSSOP |
| 標(biāo)準(zhǔn)包裝： | 50 |
| 類型： | 收發(fā)器 |
| 驅(qū)動(dòng)器/接收器數(shù)： | 6/10 |
| 規(guī)程： | RS232 |
| 電源電壓： | 10.8 V ~ 13.2 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 38-TFSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 38-TSSOP |
| 包裝： | 管件 |
10
Exar Corporation 48720 Kato Road, Fremont CA, 94538 510-668-7017 www.exar.com
SP2209E_100_071612
Phase 1
— V
DD charge storage — S1 and S2 are
closed. S3 and S4 are open. During this
phase of the clock cycle, the positive side of
C
1 is connected to GND. The negative side
of capacitor C
2 is now 2 times VCC.
Phase 2
— V
DD transfer — S1 and S2 are closed.
S3 and S4 are open. The negative side of
capacitor C
2 is connected to C2-, The posi-
tive side of C
2 is connected to GND. This
transfers a negative generated voltage to
C
2. A negative voltage is built up on the
negative side of C
2 with each cycle of the
oscillator. If the current drawn is small, the
output voltage at C
2- will be close to -Vdd.
As the current drawn from C
2- increases, the
output voltage will decrease with magnitude.
The charge pump cycle will continue as long
as the operational conditions for the internal
oscillator present. Refer to Figure 8 for the
internal charge pump waveforms.
Figure 9 Internal Standby Detection Circuit
DESCRIPTION
Figure 8. Charge Pump Waveforms
Standby Circuitry
The
SP2209E device incorporates power
saving, on board standby circuitry. The
standby current is typically less than
100A. The
SP2209E device automati-
cally enters a standby mode when the V
DD
power supply is removed. An internal com-
parator generates an internal shutdown
signal that disables the external oscillator
disengaging the charge pump. Refer to
Figure 9 for the internal standby detection
circuit.
The inverted output V- goes to ground.
All driver outputs are disabled. The inputs
for receivers 1 through 4 for both ports A
and B are at high impedance. Receiver 5
for both ports A and B remain fully active
as power management receiver lines to
system peripherals that may come online
during the standby mode.
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