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參數(shù)資料
| 型號(hào)： | SNJ54LV74AW |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS |
| 中文描述： | 雙上升沿觸發(fā)的D型觸發(fā)器 |
| 文件頁數(shù)： | 2/16頁 |
| 文件大?。?/td> | 445K |
| 代理商： | SNJ54LV74AW |
SCLS381L AUGUST 1997 REVISED APRIL 2005
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description/ordering information (continued)
A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the
other inputs. When PRE and CLR are inactive (high), data at the data (D) inputs meeting the setup-time
requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs
at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval,
data at the D input can be changed without affecting the levels at the outputs.
These devices are fully specified for partial-power-down applications using I
off
. The I
off
circuitry disables the
outputs, preventing damaging current backflow through the devices when they are powered down.
FUNCTION TABLE
INPUTS
OUTPUTS
PRE
CLR
CLK
D
Q
Q
L
H
X
X
H
L
H
L
X
X
L
H
H
L
L
X
↑
↑
L
X
H
H
H
H
H
L
H
H
L
L
H
H
H
X
Q0
Q0
This configuration is nonstable; that is, it does not
persist when PRE or CLR returns to its inactive
(high) level.
logic diagram, each flip-flop (positive logic)
TG
C
C
TG
C
TG
C
C
C
C
TG
C
C
PRE
CLK
D
CLR
Q
Q
C
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