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參數(shù)資料
| 型號： | SNJ54LV594AFK |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 8-BIT SHIFT REGISTERS WITH OUTPUT REGISTERS |
| 中文描述： | 8位移位寄存器與輸出寄存器 |
| 文件頁數(shù)： | 7/20頁 |
| 文件大小： | 440K |
| 代理商： | SNJ54LV594AFK |
SCLS413I APRIL 1998 REVISED APRIL 2005
7
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
timing requirements over recommended operating free-air temperature range, V
CC
= 2.5 V
±
0.2 V
(unless otherwise noted) (see Figure 1)
TA = 25
°
C
MIN
7
SN54LV594A
MIN
7.5
SN74LV594A
MIN
7.5
UNIT
MAX
MAX
MAX
tw
Pulse duration
RCLK or SRCLK high or low
ns
RCLR or SRCLR low
SER before SRCLK
↑
SRCLK
↑
before RCLK
↑
SRCLR low before RCLK
↑
SRCLR high (inactive) before SRCLK
↑
RCLR high (inactive) before RCLK
↑
SER after SRCLK
↑
6
6.5
6.5
5.5
5.5
5.5
8
9
9
tsu
Setup time
8.5
9.5
9.5
ns
6
6.8
6.8
6.7
7.6
7.6
th
Hold time
1.5
1.5
1.5
ns
This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case the shift
register is one clock pulse ahead of the storage register.
timing requirements over recommended operating free-air temperature range, V
CC
= 3.3 V
±
0.3 V
(unless otherwise noted) (see Figure 1)
TA = 25
°
C
MIN
5.5
SN54LV594A
MIN
5.5
SN74LV594A
MIN
5.5
UNIT
MAX
MAX
MAX
tw
Pulse duration
RCLK or SRCLK high or low
ns
RCLR or SRCLR low
SER before SRCLK
↑
SRCLK
↑
before RCLK
↑
SRCLR low before RCLK
↑
SRCLR high (inactive) before SRCLK
↑
RCLR high (inactive) before RCLK
↑
SER after SRCLK
↑
5
5
5
3.5
3.5
3.5
8
8.5
8.5
tsu
Setup time
8
9
9
ns
4.2
4.8
4.8
4.6
5.3
5.3
th
Hold time
1.5
1.5
1.5
ns
This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case the shift
register is one clock pulse ahead of the storage register.
timing requirements over recommended operating free-air temperature range, V
CC
= 5 V
±
0.5 V
(unless otherwise noted) (see Figure 1)
TA = 25
°
C
MIN
5
SN54LV594A
MIN
5
SN74LV594A
MIN
5
UNIT
MAX
MAX
MAX
tw
Pulse duration
RCLK or SRCLK high or low
ns
RCLR or SRCLR low
SER before SRCLK
↑
SRCLK
↑
before RCLK
↑
SRCLR low before RCLK
↑
SRCLR high (inactive) before SRCLK
↑
RCLR high (inactive) before RCLK
↑
SER after SRCLK
↑
5.2
5.2
5.2
3
3
3
5
5
5
tsu
Setup time
5
5
5
ns
2.9
3.3
3.3
3.2
3.7
3.7
th
Hold time
2
2
2
ns
This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case the shift
register is one clock pulse ahead of the storage register.
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