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參數(shù)資料
| 型號(hào)： | SNJ54LV373AJ |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 通用總線功能 |
| 英文描述： | OCTAL TRANSPARENT D-TYPE LATCHES WITH 3 STATE OUTPUTS |
| 中文描述： | 八路透明D類3態(tài)輸出鎖存 |
| 文件頁(yè)數(shù)： | 2/17頁(yè) |
| 文件大?。?/td> | 518K |
| 代理商： | SNJ54LV373AJ |
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SCLS407J APRIL 1998 REVISED APRIL 2005
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description/ordering information (continued)
While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the
Q outputs are latched at the logic levels set up at the D inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines
significantly. The high-impedance state and increased drive provide the capability to drive bus lines without
need for interface or pullup components.
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
These devices are fully specified for partial-power-down applications using I
off
. The I
off
circuitry disables the
outputs, preventing damaging current backflow through the devices when they are powered down.
terminal assignments
1
2
3
4
A
1Q
OE
VCC
1D
8Q
B
2D
7D
8D
C
3Q
2Q
6Q
7Q
D
4D
5D
3D
6D
E
GND
4Q
LE
5Q
FUNCTION TABLE
(each latch)
INPUTS
LE
OUTPUT
Q
OE
D
L
H
H
H
L
H
L
L
L
L
X
Q0
Z
H
X
X
logic diagram (positive logic)
OE
To Seven Other Channels
1
11
3
2
LE
1D
C1
1D
1Q
Pin numbers shown are for the DB, DGV, DW, FK, J, NS, PW, RGY, and W packages.
GQN PACKAGE
(TOP VIEW)
1
2
3
4
A
B
C
D
E
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