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參數(shù)資料
| 型號： | SNJ54LV164AJ |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 通用總線功能 |
| 英文描述： | Small Signal NPN General Purpose Transistor; Package: SOT-23 (TO-236) 3 LEAD; No of Pins: 3; Container: Tape and Reel; Qty per Container: 3000 |
| 中文描述： | 8位并行的串行移位寄存器 |
| 文件頁數(shù)： | 2/17頁 |
| 文件大?。?/td> | 464K |
| 代理商： | SNJ54LV164AJ |
SCLS403H APRIL 1998 REVISED APRIL 2005
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description/ordering information (continued)
These devices feature AND-gated serial (A and B) inputs and an asynchronous clear (CLR) input. The gated
serial inputs permit complete control over incoming data, as a low at either input inhibits entry of the new data
and resets the first flip-flop to the low level at the next clock pulse. A high-level input enables the other input,
which then determines the state of the first flip-flop. Data at the serial inputs can be changed while the clock
is high or low, provided the minimum setup time requirements are met. Clocking occurs on the low-to-high-level
transition of the clock (CLK) input.
FUNCTION TABLE
INPUTS
OUTPUTS
CLR
CLK
A
B
QA
L
QB. . . QH
L
L
X
X
X
L
H
L
↑
↑
↑
X
X
QA0
H
QB0
QAn
QAn
QAn
QH0
QGn
QGn
QGn
H
H
H
H
L
X
L
H
X
L
L
QA0, QB0, QH0 = the level of QA, QB, or QH, respectively,
before the indicated steady-state input conditions were
established.
QAn, QGn = the level of QA or QG before the most recent
↑
transition of the clock: indicates a 1-bit shift.
logic diagram (positive logic)
C1
1D
R
C1
1D
R
QA
QB
C1
1D
R
C1
1D
R
QC
QD
C1
1D
R
C1
1D
R
QE
QF
C1
1D
R
C1
1D
R
QG
QH
3
4
5
6
10
11
12
13
8
1
2
9
CLK
A
B
CLR
Pin numbers shown are for the D, DB, DGV, J, NS, PW, RGY, and W packages.
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