參數(shù)資料
型號(hào)： SNJ54HCT573W
廠商： Texas Instruments, Inc.
元件分類： 通用總線功能
英文描述： OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
中文描述： 有三態(tài)輸出的8個(gè)透明D型鎖存器
文件頁(yè)數(shù)： 1/11頁(yè)
文件大小： 370K
代理商： SNJ54HCT573W
SN54HCT573, SN74HCT573
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS176E – MARCH 1984 – REVISED JULY 2003
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Operating Voltage Range of 4.5 V to 5.5 V
High-Current 3-State Outputs Drive Bus
Lines Directly or Up To 15 LSTTL Loads
Low Power Consumption, 80-
μ
A Max I
CC
Typical t
pd
= 21 ns
±
6-mA Output Drive at 5 V
Low Input Current of 1
μ
A Max
Inputs Are TTL-Voltage Compatible
Bus-Structured Pinout
description/ordering information
These octal transparent D-type latches feature
3-state outputs designed specifically for driving
highly capacitive or relatively low-impedance
loads. The ’HCT573 devices are particularly
suitable for implementing buffer registers, I/O
ports, bidirectional bus drivers, and working
registers.
While the latch-enable (LE) input is high, the
Q outputs respond to the data (D) inputs. When
LE is low, the outputs are latched to retain the data
that was set up at the D inputs.
A buffered output-enable (OE) input can be used
to place the eight outputs in either a normal logic
state (high or low logic levels) or the
high-impedance state. In the high-impedance
state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased
drive provide the capability to drive bus lines without interface or pullup components.
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP – N
Tube
SN74HCT573N
SN74HCT573N
SOIC – DW
Tube
SN74HCT573DW
HCT573
Tape and reel
SN74HCT573DWR
–40
°
C to 85
°
C
SOP – NS
Tape and reel
SN74HCT573NSR
HCT573
SSOP – DB
Tape and reel
SN74HCT573DBR
HT573
TSSOP – PW
Tube
SN74HCT573PW
HT573
Tape and reel
SN74HCT573PWR
CDIP – J
Tube
SNJ54HCT573J
SNJ54HCT573J
–55
°
C to 125
°
C
CFP – W
Tube
SNJ54HCT573W
SNJ54HCT573W
LCCC – FK
Tube
SNJ54HCT573FK
SNJ54HCT573FK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
3
2 1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
2Q
3Q
4Q
5Q
6Q
3D
4D
5D
6D
7D
2
1
O
8
7
V
1
8
G
L
SN54HCT573 . . . FK PACKAGE
(TOP VIEW)
SN54HCT573 . . . J OR W PACKAGE
SN74HCT573 . . . DB, DW, N, NS, OR PW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OE
1D
2D
3D
4D
5D
6D
7D
8D
GND
V
CC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
LE
Copyright
2003, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
相關(guān)PDF資料
PDF描述
SNJ54HCT573FK OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
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