參數(shù)資料
型號(hào)： SNJ54AC564W
廠商： Texas Instruments, Inc.
英文描述： OCTAL D-TYPE EDGE-TRIGGERDE FLIP-FLOPS WITH 3-STATE OUTPUTS
中文描述： 八路D型EDGE的TRIGGERDE倒裝3觸發(fā)器態(tài)輸出
文件頁數(shù)： 1/13頁
文件大?。?/td> 388K
代理商： SNJ54AC564W
SCAS551D NOVEMBER 1995 REVISED OCTOBER 2003
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
2-V to 6-V V
CC
Operation
Inputs Accept Voltages to 6 V
Max t
pd
of 9 ns at 5 V
3-State Inverting Outputs Drive Bus Lines
Directly
Full Parallel Access for Loading
Flow-Through Architecture to Optimize
PCB Layout
description/ordering information
The
edge-triggered flip-flops that feature inverting
3-state outputs designed specifically for driving
highly capacitive or relatively low-impedance
loads. They are particularly suitable for
implementing
buffer
bidirectional bus drivers, and working registers.
’AC564
devices
are
octal
D-type
registers,
I/O
ports,
On the positive transition of the clock (CLK) input,
the Q outputs are set to the inverse logic levels set
up at the data (D) inputs.
A buffered output-enable (OE) input places the
eight outputs in either a normal logic state (high or
low logic levels) or the high-impedance state. In
the high-impedance state, the outputs neither
load nor drive the bus lines significantly. The
high-impedance state and increased drive
provide the capability to drive bus lines without
interface or pullup components.
OE does not affect internal operations of the flip-flops. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP N
Tube
SN74AC564N
SN74AC564N
SOIC DW
Tube
SN74AC564DW
AC564
Tape and reel
SN74AC564DWR
40 C to 85 C
SOP NS
Tape and reel
SN74AC564NSR
AC564
SSOP DB
Tape and reel
SN74AC564DBR
AC564
TSSOP PW
Tube
SN74AC564PW
AC564
Tape and reel
SN74AC564PWR
CDIP J
Tube
SNJ54AC564J
SNJ54AC564J
55 C to 125 C
CFP W
Tube
SNJ54AC564W
SNJ54AC564W
LCCC FK
Tube
SNJ54AC564FK
SNJ54AC564FK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OE
1D
2D
3D
4D
5D
6D
7D
8D
GND
V
CC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
CLK
SN54AC564 . . . J OR W PACKAGE
SN74AC564 . . . DB, DW, N, NS, OR PW PACKAGE
(TOP VIEW)
3
2
1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
2Q
3Q
4Q
5Q
6Q
3D
4D
5D
6D
7D
2
1
O
8
7
1
8
G
C
V
C
SN54AC564 . . . FK PACKAGE
(TOP VIEW)
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Copyright
2003, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SNJ54AC573FK 制造商:TI 制造商全稱:Texas Instruments 功能描述:OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS
SNJ54AC573J 制造商:TI 制造商全稱:Texas Instruments 功能描述:OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS
SNJ54AC573W 制造商:TI 制造商全稱:Texas Instruments 功能描述:OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS
SNJ54AC574FK 制造商:TI 制造商全稱:Texas Instruments 功能描述:OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS
SNJ54AC574J 制造商:Texas Instruments 功能描述:
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